MLK-10175 arm: imx6: Skip gating QSPI2 clk when M4 is enabled

When the M4 core is enabled on i.MX6, the QSPI2 clk can't be gated,
otherwise, the M4 will hang. This patch add a check to make sure when
M4 is enabled, just skip the QSPI2 clk gating operations.

Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit e2f1732)
(cherry picked from commit 60def702db2c083cc6c0486100a829d71dc74845)

arch/arm/mach-imx/clk-imx6sx.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -551,9 +551,10 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 	 * different gate, need explicitely gate the QSPI2 & GPMI_IO
 	 * during the clock init phase according to the SOC design.
 	 */
-	writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(5)), base + 0x78);
-	writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(14)), base + 0x78);
-
+	if (!imx_src_is_m4_enabled()) {
+		writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(5)), base + 0x78);
+		writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(14)), base + 0x78);
+	}
 	clk_data.clks = clks;
 	clk_data.clk_num = ARRAY_SIZE(clks);
 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);