Skip to content
View amsacks's full-sized avatar

Block or report amsacks

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
amsacks/README.md

Anurag's GitHub stats

Popular repositories Loading

  1. OV7670-camera OV7670-camera Public

    A RTL-based project in Verilog that shows real-time video captured by a CMOS camera OV7670 and displayed on a monitor through VGA at 640 x 480 resolution, 30 fps.

    Verilog 17 1

  2. Asynchronous-FIFO Asynchronous-FIFO Public

    RTL of a parametrized asynchronous FIFO that allows for variable depth, data width, and includes almost empty/full flags.

    Verilog 7

  3. OV7670-Video-Processing OV7670-Video-Processing Public

    Pipelined a real-time edge detection system with a OV7670 camera and Nexys A7 100T FPGA Trainer Board

    Verilog 5 2

  4. CoinCollector-FPGA-game CoinCollector-FPGA-game Public

    Final Project for ECE 3300: Digital Logic Design Using Verilog.

    Verilog 2

  5. amsacks amsacks Public

0 contributions in the last year

Skip to contributions year list
Contribution Graph
Day of Week August September October November December January February March April May June July
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
Less
No contributions.
Low contributions.
Medium-low contributions.
Medium-high contributions.
High contributions.
More

Contribution activity

July 2025

amsacks has no activity yet for this period.
Loading