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ad5791 offload #2616

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15 changes: 15 additions & 0 deletions Documentation/devicetree/bindings/iio/dac/adi,ad5791.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,17 @@ properties:
gain of two configuration.
type: boolean

reset-gpios:
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Jonathan also likes to have all of the power supplies in the bindings, so we can add vcc-suppy, vrefp-supply, vrefn-supply and iovcc-supply when we submit this upstream.

maxItems: 1

clear-gpios:
maxItems: 1

ldac-gpios:
description:
LDAC pin to be used as a hardware trigger to update the DAC channels.
maxItems: 1

required:
- compatible
- reg
Expand All @@ -44,6 +55,7 @@ unevaluatedProperties: false

examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
Expand All @@ -53,6 +65,9 @@ examples:
reg = <0>;
vss-supply = <&dac_vss>;
vdd-supply = <&dac_vdd>;
reset-gpios = <&gpio_bd 16 GPIO_ACTIVE_LOW>;
clear-gpios = <&gpio_bd 17 GPIO_ACTIVE_LOW>;
ldac-gpios = <&gpio_bd 18 GPIO_ACTIVE_HIGH>;
};
};
...
1 change: 0 additions & 1 deletion arch/arm/boot/dts/socfpga_arria10_socdk_ad9081.dts
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Expand Up @@ -54,7 +54,6 @@
sys_gpio_out: gpio@20 {
compatible = "altr,pio-1.0";
reg = <0x00000020 0x00000010>;
altr,gpio-bank-width = <32>;
resetvalue = <0>;
#gpio-cells = <2>;
gpio-controller;
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,6 @@
sys_gpio_out: gpio@20 {
compatible = "altr,pio-1.0";
reg = <0x00000020 0x00000010>;
altr,gpio-bank-width = <32>;
resetvalue = <0>;
#gpio-cells = <2>;
gpio-controller;
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1 change: 0 additions & 1 deletion arch/arm/boot/dts/socfpga_arria10_socdk_adrv9002.dts
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,6 @@
reg = <0x00060000 0x00000010>;
interrupt-parent = <&intc>;
interrupts = <0 33 4>;
altr,gpio-bank-width = <19>;
altr,interrupt-type = <4>;
altr,interrupt_type = <4>;
level_trigger = <1>;
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,6 @@
reg = <0x00060000 0x00000010>;
interrupt-parent = <&intc>;
interrupts = <0 33 4>;
altr,gpio-bank-width = <19>;
altr,interrupt-type = <4>;
altr,interrupt_type = <4>;
level_trigger = <1>;
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1 change: 0 additions & 1 deletion arch/arm/boot/dts/socfpga_arria10_socdk_adrv9009.dts
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,6 @@
sys_gpio_out: gpio@20 {
compatible = "altr,pio-1.0";
reg = <0x00000020 0x00000010>;
altr,gpio-bank-width = <32>;
resetvalue = <0>;
#gpio-cells = <2>;
gpio-controller;
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1 change: 0 additions & 1 deletion arch/arm/boot/dts/socfpga_arria10_socdk_adrv9025.dts
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,6 @@
sys_gpio_out: gpio@20 {
compatible = "altr,pio-1.0";
reg = <0x00000020 0x00000010>;
altr,gpio-bank-width = <32>;
resetvalue = <0>;
#gpio-cells = <2>;
gpio-controller;
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1 change: 0 additions & 1 deletion arch/arm/boot/dts/socfpga_arria10_socdk_adrv9371.dts
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,6 @@
sys_gpio_out: gpio@20 {
compatible = "altr,pio-1.0";
reg = <0x00000020 0x00000010>;
altr,gpio-bank-width = <32>;
resetvalue = <0>;
#gpio-cells = <2>;
gpio-controller;
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1 change: 0 additions & 1 deletion arch/arm/boot/dts/socfpga_arria10_socdk_fmcomms8.dts
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,6 @@
sys_gpio_out: gpio@20 {
compatible = "altr,pio-1.0";
reg = <0x00000020 0x00000010>;
altr,gpio-bank-width = <32>;
resetvalue = <0>;
#gpio-cells = <2>;
gpio-controller;
Expand Down
107 changes: 107 additions & 0 deletions arch/arm/boot/dts/socfpga_cyclone5_de10_nano_ad57xx.dts
Original file line number Diff line number Diff line change
@@ -0,0 +1,107 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices AD5791
* https://www.analog.com/en/products/ad5791.html
* https://analogdevicesinc.github.io/hdl/projects/ad57xx_ardz/index.html
* https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD5791ARDZ.html
* https://wiki.analog.com/resources/tools-software/linux-build/generic/socfpga
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*
* hdl_project: <ad57xx_ardz/de10nano>
* board_revision: <B>
*
* Copyright (C) 2024 Analog Devices Inc.
*/
/dts-v1/;
#include "socfpga_cyclone5_de10_nano_hps.dtsi"
#include <dt-bindings/dma/axi-dmac.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

/ {
dac_vdd: regulator-vdd {
compatible = "regulator-fixed";
regulator-name = "fixed-supply";
regulator-min-microvolt = <4096000>;
regulator-max-microvolt = <4096000>;
regulator-always-on;
};

dac_vss: regulator-vss {
compatible = "regulator-fixed";
regulator-name = "fixed-supply";
regulator-min-microvolt = <4096000>;
regulator-max-microvolt = <4096000>;
regulator-always-on;
};

};

&fpga_axi {

adc_trigger: pwm@0x00050000 {
compatible = "adi,axi-pwmgen-2.00.a";
reg = <0x00050000 0x1000>;
#pwm-cells = <2>;
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ok.

clocks = <&spi_clk 0>;
};

tx_dma: tx-dma@0x00030000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x00030000 0x00000800>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&spi_clk 0>;
};

spi_clk: clock-controller@0x00060000 {
compatible = "altr,c5-fpll";
reg = <0x00060000 0x00000100>;
#clock-cells = <0x1>;

#address-cells = <1>;
#size-cells = <0>;
clocks = <&sys_clk>;
assigned-clocks = <&spi_clk 0>;
assigned-clock-rates = <185000000>;
clock-output-names = "outclk0";
adi,fractional-carry-bit = <32>;

spi_c0: channel@0 {
reg = <0>;
adi,extended-name = "SPI_CLOCK";
};
};

spi@0x00040000 {
compatible = "adi-ex,axi-spi-engine-1.00.a";
reg = <0x00040000 0x00010000>;
interrupt-parent = <&intc>;
interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_clk>, <&spi_clk 0>;
clock-names = "s_axi_aclk", "spi_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;

ad57xx_1: dac@0 {
compatible = "adi,ad5791";
spi-cpha;
reg = <0>;
spi-max-frequency = <35000000>;
vss-supply = <&dac_vss>;
vdd-supply = <&dac_vdd>;
reset-gpios = <&gpio_bd 16 GPIO_ACTIVE_LOW>;
clear-gpios = <&gpio_bd 17 GPIO_ACTIVE_LOW>;
ldac-gpios = <&gpio_bd 18 GPIO_ACTIVE_LOW>;

clocks = <&spi_clk 0>;
clock-names = "ref_clk";

dmas = <&tx_dma 0>;
dma-names = "tx";
pwms = <&adc_trigger 0 0>;
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How unusual to have the default period 0. I'd rather expect to see a period that matches the max freq for that chip here (or something bigger).

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ok. just for the record, i could not clearly make out a max frequency clearly mentioned on the datasheet.
only the spi speed of 35Mbps is mentioned. if we calculate 24 bits, i think a sample rate of 1Mbps is "reasonable"

pwm-names = "cnv";

};
};
};
10 changes: 8 additions & 2 deletions arch/arm/boot/dts/socfpga_cyclone5_de10_nano_hps.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -31,10 +31,17 @@
};

&fpga_axi {
gpio_bd: gpio_bd@0x00010080 {
compatible = "altr,pio-18.1", "altr,pio-1.0";
reg = <0x00010080 0x00000010>;
resetvalue = <0>;
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#gpio-cells = <2>;
gpio-controller;
};

gpio_in: gpio_in@0x00010100 {
compatible = "altr,pio-18.1", "altr,pio-1.0";
reg = <0x00010100 0x00000010>;
altr,gpio-bank-width = <32>;
altr,interrupt-type = <4>;
altr,interrupt_type = <4>;
level_trigger = <1>;
Expand Down Expand Up @@ -107,7 +114,6 @@
gpio_out: gpio_out@0x00109000 {
compatible = "altr,pio-1.0";
reg = <0x00109000 0x00000010>;
altr,gpio-bank-width = <32>;
resetvalue = <0>;
#gpio-cells = <2>;
gpio-controller;
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1 change: 0 additions & 1 deletion arch/arm/boot/dts/socfpga_cyclone5_sockit_arradio.dts
Original file line number Diff line number Diff line change
Expand Up @@ -172,7 +172,6 @@
gpio: gpio@9000 {
compatible = "altr,pio-1.0";
reg = <0x00009000 0x00000010>;
altr,gpio-bank-width = <5>;
resetvalue = <0>;
#gpio-cells = <2>;
gpio-controller;
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1 change: 0 additions & 1 deletion arch/arm/boot/dts/socfpga_cyclone5_sockit_dc2677a.dts
Original file line number Diff line number Diff line change
Expand Up @@ -145,7 +145,6 @@
gpio: gpio@9000 {
compatible = "altr,pio-1.0";
reg = <0x00020000 0x00010000>;
altr,gpio-bank-width = <5>;
resetvalue = <0>;
#gpio-cells = <2>;
gpio-controller;
Expand Down
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