Calyx AXI Example

Working Calyx AXI example. I just manually fixed the verilog, still need fixes to the generators obviously.

The src directory has the working code and src_default has what is generated by Calyx. I would suggest diffing the files in these folders to get an understanding of the fixes I made.

Build

make

Running

You can run the design either of the following ways:

PYNQ

python dot-product.py

fud

fud e ./build/kernel.xclbin --from xclbin --to fpga -s fpga.data ../calyx/examples/dahlia/dot-product.fuse.data