Add a submodule for storing verilog code and generated expressions

anikau31 · Jan 10, 2020 · cf66157 · cf66157
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diff --git a/.gitmodules b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "tests/data/verilog-conversion"]
+	path = tests/data/verilog-conversion
+	url = git@github.com:zhuanhao-wu/systemc-clang-verilog-conversion.git
diff --git a/tests/data/verilog-conversion b/tests/data/verilog-conversion