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[mi-sched] Suppress register pressure with i64. (llvm#88256)
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Machine scheduler will suppress register pressure when the scheduling
window is too small, but now it doesn't consider i64 register type,
and this MR extends it into i64 register type, so architecture like
RISCV64 that only supports i64 interger register will have the same
behavior like RISCV32.
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@lcvon007
lcvon007 authored Apr 15, 2024
1 parent 7177dc2 commit 6b80e2f
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Showing 14 changed files with 255 additions and 366 deletions.
6 changes: 4 additions & 2 deletions llvm/lib/CodeGen/MachineScheduler.cpp
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Expand Up @@ -3281,14 +3281,16 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,

// Avoid setting up the register pressure tracker for small regions to save
// compile time. As a rough heuristic, only track pressure when the number of
// schedulable instructions exceeds half the integer register file.
// schedulable instructions exceeds half the allocatable integer register file
// that is the largest legal integer regiser type.
RegionPolicy.ShouldTrackPressure = true;
for (unsigned VT = MVT::i32; VT > (unsigned)MVT::i1; --VT) {
for (unsigned VT = MVT::i64; VT > (unsigned)MVT::i1; --VT) {
MVT::SimpleValueType LegalIntVT = (MVT::SimpleValueType)VT;
if (TLI->isTypeLegal(LegalIntVT)) {
unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
TLI->getRegClassFor(LegalIntVT));
RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
break;
}
}

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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll
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Expand Up @@ -4,12 +4,12 @@
define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
; LA64-LABEL: atomicrmw_uinc_wrap_i8:
; LA64: # %bb.0:
; LA64-NEXT: slli.d $a2, $a0, 3
; LA64-NEXT: slli.d $a4, $a0, 3
; LA64-NEXT: bstrins.d $a0, $zero, 1, 0
; LA64-NEXT: ori $a3, $zero, 255
; LA64-NEXT: sll.w $a4, $a3, $a2
; LA64-NEXT: andi $a2, $a4, 24
; LA64-NEXT: ori $a5, $zero, 255
; LA64-NEXT: ld.w $a3, $a0, 0
; LA64-NEXT: andi $a2, $a2, 24
; LA64-NEXT: sll.w $a4, $a5, $a4
; LA64-NEXT: nor $a4, $a4, $zero
; LA64-NEXT: andi $a1, $a1, 255
; LA64-NEXT: .p2align 4, , 16
Expand Down Expand Up @@ -54,13 +54,13 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) {
; LA64-LABEL: atomicrmw_uinc_wrap_i16:
; LA64: # %bb.0:
; LA64-NEXT: slli.d $a2, $a0, 3
; LA64-NEXT: slli.d $a4, $a0, 3
; LA64-NEXT: bstrins.d $a0, $zero, 1, 0
; LA64-NEXT: andi $a2, $a4, 24
; LA64-NEXT: lu12i.w $a3, 15
; LA64-NEXT: ori $a3, $a3, 4095
; LA64-NEXT: sll.w $a4, $a3, $a2
; LA64-NEXT: ori $a5, $a3, 4095
; LA64-NEXT: ld.w $a3, $a0, 0
; LA64-NEXT: andi $a2, $a2, 24
; LA64-NEXT: sll.w $a4, $a5, $a4
; LA64-NEXT: nor $a4, $a4, $zero
; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-NEXT: .p2align 4, , 16
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18 changes: 9 additions & 9 deletions llvm/test/CodeGen/LoongArch/vector-fp-imm.ll
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Expand Up @@ -124,10 +124,10 @@ define void @test_f2(ptr %P, ptr %S) nounwind {
; LA64F: # %bb.0:
; LA64F-NEXT: fld.s $fa0, $a0, 4
; LA64F-NEXT: fld.s $fa1, $a0, 0
; LA64F-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
; LA64F-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI1_0)
; LA64F-NEXT: fld.s $fa2, $a0, 0
; LA64F-NEXT: addi.w $a0, $zero, 1
; LA64F-NEXT: pcalau12i $a2, %pc_hi20(.LCPI1_0)
; LA64F-NEXT: addi.d $a2, $a2, %pc_lo12(.LCPI1_0)
; LA64F-NEXT: fld.s $fa2, $a2, 0
; LA64F-NEXT: movgr2fr.w $fa3, $a0
; LA64F-NEXT: ffint.s.w $fa3, $fa3
; LA64F-NEXT: fadd.s $fa1, $fa1, $fa3
Expand All @@ -140,10 +140,10 @@ define void @test_f2(ptr %P, ptr %S) nounwind {
; LA64D: # %bb.0:
; LA64D-NEXT: fld.s $fa0, $a0, 4
; LA64D-NEXT: fld.s $fa1, $a0, 0
; LA64D-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
; LA64D-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI1_0)
; LA64D-NEXT: fld.s $fa2, $a0, 0
; LA64D-NEXT: addi.w $a0, $zero, 1
; LA64D-NEXT: pcalau12i $a2, %pc_hi20(.LCPI1_0)
; LA64D-NEXT: addi.d $a2, $a2, %pc_lo12(.LCPI1_0)
; LA64D-NEXT: fld.s $fa2, $a2, 0
; LA64D-NEXT: movgr2fr.w $fa3, $a0
; LA64D-NEXT: ffint.s.w $fa3, $fa3
; LA64D-NEXT: fadd.s $fa1, $fa1, $fa3
Expand Down Expand Up @@ -527,10 +527,10 @@ define void @test_d2(ptr %P, ptr %S) nounwind {
; LA64D: # %bb.0:
; LA64D-NEXT: fld.d $fa0, $a0, 8
; LA64D-NEXT: fld.d $fa1, $a0, 0
; LA64D-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
; LA64D-NEXT: addi.d $a0, $a0, %pc_lo12(.LCPI4_0)
; LA64D-NEXT: fld.d $fa2, $a0, 0
; LA64D-NEXT: addi.d $a0, $zero, 1
; LA64D-NEXT: pcalau12i $a2, %pc_hi20(.LCPI4_0)
; LA64D-NEXT: addi.d $a2, $a2, %pc_lo12(.LCPI4_0)
; LA64D-NEXT: fld.d $fa2, $a2, 0
; LA64D-NEXT: movgr2fr.d $fa3, $a0
; LA64D-NEXT: ffint.d.l $fa3, $fa3
; LA64D-NEXT: fadd.d $fa1, $fa1, $fa3
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
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Expand Up @@ -127,11 +127,11 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
; RV64IA-LABEL: atomicrmw_uinc_wrap_i8:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slli a0, a0, 3
; RV64IA-NEXT: li a3, 255
; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: slli a4, a0, 3
; RV64IA-NEXT: andi a0, a4, 24
; RV64IA-NEXT: li a5, 255
; RV64IA-NEXT: lw a3, 0(a2)
; RV64IA-NEXT: andi a0, a0, 24
; RV64IA-NEXT: sllw a4, a5, a4
; RV64IA-NEXT: not a4, a4
; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: .LBB0_1: # %atomicrmw.start
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/bfloat-convert.ll
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Expand Up @@ -84,12 +84,12 @@ define i16 @fcvt_si_bf16_sat(bfloat %a) nounwind {
; CHECK64ZFBFMIN: # %bb.0: # %start
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: feq.s a0, fa5, fa5
; CHECK64ZFBFMIN-NEXT: neg a0, a0
; CHECK64ZFBFMIN-NEXT: lui a1, %hi(.LCPI1_0)
; CHECK64ZFBFMIN-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
; CHECK64ZFBFMIN-NEXT: lui a1, 815104
; CHECK64ZFBFMIN-NEXT: fmv.w.x fa3, a1
; CHECK64ZFBFMIN-NEXT: fmax.s fa5, fa5, fa3
; CHECK64ZFBFMIN-NEXT: neg a0, a0
; CHECK64ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a1, fa5, rtz
; CHECK64ZFBFMIN-NEXT: and a0, a0, a1
Expand Down Expand Up @@ -187,10 +187,10 @@ define i16 @fcvt_ui_bf16_sat(bfloat %a) nounwind {
;
; RV64ID-LABEL: fcvt_ui_bf16_sat:
; RV64ID: # %bb.0: # %start
; RV64ID-NEXT: lui a0, %hi(.LCPI3_0)
; RV64ID-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
; RV64ID-NEXT: fmv.x.w a0, fa0
; RV64ID-NEXT: slli a0, a0, 16
; RV64ID-NEXT: lui a1, %hi(.LCPI3_0)
; RV64ID-NEXT: flw fa5, %lo(.LCPI3_0)(a1)
; RV64ID-NEXT: fmv.w.x fa4, a0
; RV64ID-NEXT: fmv.w.x fa3, zero
; RV64ID-NEXT: fmax.s fa4, fa4, fa3
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
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Expand Up @@ -140,11 +140,11 @@ define i64 @caller_large_scalars() nounwind {
; RV64I-NEXT: sd a0, 0(sp)
; RV64I-NEXT: sd zero, 56(sp)
; RV64I-NEXT: sd zero, 48(sp)
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: sd a0, 32(sp)
; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: addi a0, sp, 32
; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: sd a2, 32(sp)
; RV64I-NEXT: call callee_large_scalars
; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 80
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28 changes: 14 additions & 14 deletions llvm/test/CodeGen/RISCV/double-convert.ll
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Expand Up @@ -1651,8 +1651,8 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV64IFD-NEXT: lui a0, %hi(.LCPI26_1)
; RV64IFD-NEXT: fld fa4, %lo(.LCPI26_1)(a0)
; RV64IFD-NEXT: feq.d a0, fa0, fa0
; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
; RV64IFD-NEXT: neg a0, a0
; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
; RV64IFD-NEXT: fmin.d fa5, fa5, fa4
; RV64IFD-NEXT: fcvt.l.d a1, fa5, rtz
; RV64IFD-NEXT: and a0, a0, a1
Expand Down Expand Up @@ -1680,12 +1680,12 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI26_0)(a1)
; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_1)
; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI26_1)(a2)
; RV64IZFINXZDINX-NEXT: fmax.d a1, a0, a1
; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV64IZFINXZDINX-NEXT: neg a0, a0
; RV64IZFINXZDINX-NEXT: fmin.d a1, a1, a2
; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a1, rtz
; RV64IZFINXZDINX-NEXT: and a0, a0, a1
; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
; RV64IZFINXZDINX-NEXT: neg a3, a3
; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
; RV64IZFINXZDINX-NEXT: and a0, a3, a0
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i16:
Expand Down Expand Up @@ -2026,8 +2026,8 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV64IFD-NEXT: lui a0, %hi(.LCPI30_1)
; RV64IFD-NEXT: fld fa4, %lo(.LCPI30_1)(a0)
; RV64IFD-NEXT: feq.d a0, fa0, fa0
; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
; RV64IFD-NEXT: neg a0, a0
; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
; RV64IFD-NEXT: fmin.d fa5, fa5, fa4
; RV64IFD-NEXT: fcvt.l.d a1, fa5, rtz
; RV64IFD-NEXT: and a0, a0, a1
Expand Down Expand Up @@ -2055,12 +2055,12 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI30_0)(a1)
; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_1)
; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI30_1)(a2)
; RV64IZFINXZDINX-NEXT: fmax.d a1, a0, a1
; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
; RV64IZFINXZDINX-NEXT: neg a0, a0
; RV64IZFINXZDINX-NEXT: fmin.d a1, a1, a2
; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a1, rtz
; RV64IZFINXZDINX-NEXT: and a0, a0, a1
; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
; RV64IZFINXZDINX-NEXT: neg a3, a3
; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
; RV64IZFINXZDINX-NEXT: and a0, a3, a0
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i8:
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/float-convert.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1424,12 +1424,12 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV64IF-LABEL: fcvt_w_s_sat_i16:
; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: neg a0, a0
; RV64IF-NEXT: lui a1, %hi(.LCPI24_0)
; RV64IF-NEXT: flw fa5, %lo(.LCPI24_0)(a1)
; RV64IF-NEXT: lui a1, 815104
; RV64IF-NEXT: fmv.w.x fa4, a1
; RV64IF-NEXT: fmax.s fa4, fa0, fa4
; RV64IF-NEXT: neg a0, a0
; RV64IF-NEXT: fmin.s fa5, fa4, fa5
; RV64IF-NEXT: fcvt.l.s a1, fa5, rtz
; RV64IF-NEXT: and a0, a0, a1
Expand All @@ -1450,15 +1450,15 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
;
; RV64IZFINX-LABEL: fcvt_w_s_sat_i16:
; RV64IZFINX: # %bb.0: # %start
; RV64IZFINX-NEXT: lui a1, 815104
; RV64IZFINX-NEXT: feq.s a1, a0, a0
; RV64IZFINX-NEXT: lui a2, %hi(.LCPI24_0)
; RV64IZFINX-NEXT: lw a2, %lo(.LCPI24_0)(a2)
; RV64IZFINX-NEXT: fmax.s a1, a0, a1
; RV64IZFINX-NEXT: feq.s a0, a0, a0
; RV64IZFINX-NEXT: neg a0, a0
; RV64IZFINX-NEXT: fmin.s a1, a1, a2
; RV64IZFINX-NEXT: fcvt.l.s a1, a1, rtz
; RV64IZFINX-NEXT: and a0, a0, a1
; RV64IZFINX-NEXT: neg a1, a1
; RV64IZFINX-NEXT: lui a3, 815104
; RV64IZFINX-NEXT: fmax.s a0, a0, a3
; RV64IZFINX-NEXT: fmin.s a0, a0, a2
; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz
; RV64IZFINX-NEXT: and a0, a1, a0
; RV64IZFINX-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i16:
Expand Down
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