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Precommit tests for overflowing and saturating arithmetic intrinsics.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,163 @@ | ||
| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 | ||
| ; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s | ||
|
|
||
| target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" | ||
| target triple = "x86_64-unknown-linux-gnu" | ||
|
|
||
| define {i64, i1} @test_sadd_with_overflow(i64 %a, i64 %b) #0 { | ||
| ; CHECK-LABEL: define { i64, i1 } @test_sadd_with_overflow( | ||
| ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 | ||
| ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 | ||
| ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] | ||
| ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0:![0-9]+]] | ||
| ; CHECK: 3: | ||
| ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]] | ||
| ; CHECK-NEXT: unreachable | ||
| ; CHECK: 4: | ||
| ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 [[A]], i64 [[B]]) | ||
| ; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret { i64, i1 } [[RES]] | ||
| ; | ||
| %res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) | ||
| ret { i64, i1 } %res | ||
| } | ||
|
|
||
| define {i64, i1} @test_uadd_with_overflow(i64 %a, i64 %b) #0 { | ||
| ; CHECK-LABEL: define { i64, i1 } @test_uadd_with_overflow( | ||
| ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 | ||
| ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 | ||
| ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] | ||
| ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] | ||
| ; CHECK: 3: | ||
| ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] | ||
| ; CHECK-NEXT: unreachable | ||
| ; CHECK: 4: | ||
| ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[A]], i64 [[B]]) | ||
| ; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret { i64, i1 } [[RES]] | ||
| ; | ||
| %res = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) | ||
| ret { i64, i1 } %res | ||
| } | ||
|
|
||
| define {i64, i1} @test_smul_with_overflow(i64 %a, i64 %b) #0 { | ||
| ; CHECK-LABEL: define { i64, i1 } @test_smul_with_overflow( | ||
| ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 | ||
| ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 | ||
| ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] | ||
| ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] | ||
| ; CHECK: 3: | ||
| ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] | ||
| ; CHECK-NEXT: unreachable | ||
| ; CHECK: 4: | ||
| ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 [[A]], i64 [[B]]) | ||
| ; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret { i64, i1 } [[RES]] | ||
| ; | ||
| %res = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %a, i64 %b) | ||
| ret { i64, i1 } %res | ||
| } | ||
| define {i64, i1} @test_umul_with_overflow(i64 %a, i64 %b) #0 { | ||
| ; CHECK-LABEL: define { i64, i1 } @test_umul_with_overflow( | ||
| ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 | ||
| ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 | ||
| ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] | ||
| ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] | ||
| ; CHECK: 3: | ||
| ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] | ||
| ; CHECK-NEXT: unreachable | ||
| ; CHECK: 4: | ||
| ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A]], i64 [[B]]) | ||
| ; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret { i64, i1 } [[RES]] | ||
| ; | ||
| %res = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b) | ||
| ret { i64, i1 } %res | ||
| } | ||
| define {i64, i1} @test_ssub_with_overflow(i64 %a, i64 %b) #0 { | ||
| ; CHECK-LABEL: define { i64, i1 } @test_ssub_with_overflow( | ||
| ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 | ||
| ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 | ||
| ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] | ||
| ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] | ||
| ; CHECK: 3: | ||
| ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] | ||
| ; CHECK-NEXT: unreachable | ||
| ; CHECK: 4: | ||
| ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 [[A]], i64 [[B]]) | ||
| ; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret { i64, i1 } [[RES]] | ||
| ; | ||
| %res = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) | ||
| ret { i64, i1 } %res | ||
| } | ||
| define {i64, i1} @test_usub_with_overflow(i64 %a, i64 %b) #0 { | ||
| ; CHECK-LABEL: define { i64, i1 } @test_usub_with_overflow( | ||
| ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 | ||
| ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 | ||
| ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] | ||
| ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] | ||
| ; CHECK: 3: | ||
| ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] | ||
| ; CHECK-NEXT: unreachable | ||
| ; CHECK: 4: | ||
| ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[A]], i64 [[B]]) | ||
| ; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret { i64, i1 } [[RES]] | ||
| ; | ||
| %res = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) | ||
| ret { i64, i1 } %res | ||
| } | ||
|
|
||
| define {<4 x i32>, <4 x i1>} @test_sadd_with_overflow_vec(<4 x i32> %a, <4 x i32> %b) #0 { | ||
| ; CHECK-LABEL: define { <4 x i32>, <4 x i1> } @test_sadd_with_overflow_vec( | ||
| ; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 | ||
| ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 | ||
| ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 | ||
| ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0 | ||
| ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] | ||
| ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] | ||
| ; CHECK: 5: | ||
| ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] | ||
| ; CHECK-NEXT: unreachable | ||
| ; CHECK: 6: | ||
| ; CHECK-NEXT: [[RES:%.*]] = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) | ||
| ; CHECK-NEXT: store { <4 x i32>, <4 x i1> } zeroinitializer, ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret { <4 x i32>, <4 x i1> } [[RES]] | ||
| ; | ||
| %res = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) | ||
| ret { <4 x i32>, <4 x i1> } %res | ||
| } | ||
|
|
||
| attributes #0 = { sanitize_memory } | ||
| ;. | ||
| ; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 1000} | ||
| ;. |
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llvm/test/Instrumentation/MemorySanitizer/saturating.ll
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,113 @@ | ||
| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 | ||
| ; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s | ||
|
|
||
| target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" | ||
| target triple = "x86_64-unknown-linux-gnu" | ||
|
|
||
| define i64 @test_sadd_sat(i64 %a, i64 %b) #0 { | ||
| ; CHECK-LABEL: define i64 @test_sadd_sat( | ||
| ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] | ||
| ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sadd.sat.i64(i64 [[A]], i64 [[B]]) | ||
| ; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret i64 [[RES]] | ||
| ; | ||
| %res = call i64 @llvm.sadd.sat(i64 %a, i64 %b) | ||
| ret i64 %res | ||
| } | ||
|
|
||
| define i64 @test_uadd_sat(i64 %a, i64 %b) #0 { | ||
| ; CHECK-LABEL: define i64 @test_uadd_sat( | ||
| ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] | ||
| ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[A]], i64 [[B]]) | ||
| ; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret i64 [[RES]] | ||
| ; | ||
| %res = call i64 @llvm.uadd.sat(i64 %a, i64 %b) | ||
| ret i64 %res | ||
| } | ||
|
|
||
| define i64 @test_ssub_sat(i64 %a, i64 %b) #0 { | ||
| ; CHECK-LABEL: define i64 @test_ssub_sat( | ||
| ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] | ||
| ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ssub.sat.i64(i64 [[A]], i64 [[B]]) | ||
| ; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret i64 [[RES]] | ||
| ; | ||
| %res = call i64 @llvm.ssub.sat(i64 %a, i64 %b) | ||
| ret i64 %res | ||
| } | ||
|
|
||
| define i64 @test_usub_sat(i64 %a, i64 %b) #0 { | ||
| ; CHECK-LABEL: define i64 @test_usub_sat( | ||
| ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] | ||
| ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]]) | ||
| ; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret i64 [[RES]] | ||
| ; | ||
| %res = call i64 @llvm.usub.sat(i64 %a, i64 %b) | ||
| ret i64 %res | ||
| } | ||
|
|
||
| define i64 @test_sshl_sat(i64 %a, i64 %b) #0 { | ||
| ; CHECK-LABEL: define i64 @test_sshl_sat( | ||
| ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] | ||
| ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sshl.sat.i64(i64 [[A]], i64 [[B]]) | ||
| ; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret i64 [[RES]] | ||
| ; | ||
| %res = call i64 @llvm.sshl.sat(i64 %a, i64 %b) | ||
| ret i64 %res | ||
| } | ||
|
|
||
| define i64 @test_ushl_sat(i64 %a, i64 %b) #0 { | ||
| ; CHECK-LABEL: define i64 @test_ushl_sat( | ||
| ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] | ||
| ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ushl.sat.i64(i64 [[A]], i64 [[B]]) | ||
| ; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret i64 [[RES]] | ||
| ; | ||
| %res = call i64 @llvm.ushl.sat(i64 %a, i64 %b) | ||
| ret i64 %res | ||
| } | ||
|
|
||
| define <4 x i32> @test_sadd_sat_vec(<4 x i32> %a, <4 x i32> %b) #0 { | ||
| ; CHECK-LABEL: define <4 x i32> @test_sadd_sat_vec( | ||
| ; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { | ||
| ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 | ||
| ; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 | ||
| ; CHECK-NEXT: call void @llvm.donothing() | ||
| ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] | ||
| ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) | ||
| ; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 | ||
| ; CHECK-NEXT: ret <4 x i32> [[RES]] | ||
| ; | ||
| %res = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b) | ||
| ret <4 x i32> %res | ||
| } | ||
|
|
||
|
|
||
| attributes #0 = { sanitize_memory } |