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antmicro · Jun 30, 2020 · 530879c · 530879c
1 parent da5b557
commit 530879c
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Showing 22 changed files with 77 additions and 20 deletions.
diff --git a/targets/basys3/base.py b/targets/basys3/base.py
@@ -19,7 +19,10 @@ class BaseSoC(SoCCore):
     }}
 
     def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
-        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+       if kwargs.get('cpu_type', None) == 'mor1kx':
+            dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
 
         sys_clk_freq = int(100e6)

diff --git a/targets/cmod_a7/base.py b/targets/cmod_a7/base.py
@@ -19,7 +19,10 @@ class BaseSoC(SoCCore):
     }}
 
     def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
-        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        if kwargs.get('cpu_type', None) == 'mor1kx':
+            dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
 
         sys_clk_freq = int(100e6)

diff --git a/targets/galatea/base.py b/targets/galatea/base.py
@@ -23,7 +23,10 @@ class BaseSoC(SoCSDRAM):
     }}
 
     def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
-        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        if kwargs.get('cpu_type', None) == 'mor1kx':
+            dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x4000)
 
         sys_clk_freq = 50*1000000

diff --git a/targets/matrix_voice/base.py b/targets/matrix_voice/base.py
@@ -27,7 +27,10 @@ class BaseSoC(SoCSDRAM):
     }}
 
     def __init__(self, platform, **kwargs):
-        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        if kwargs.get('cpu_type', None) == 'mor1kx':
+            dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x4000)
 
         kwargs['uart_baudrate']=230400

diff --git a/targets/mimas_a7/base.py b/targets/mimas_a7/base.py
@@ -24,9 +24,9 @@ class BaseSoC(SoCSDRAM):
 
     def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
         if kwargs.get('cpu_type', None) == "mor1kx":
-            dict_set_max(kwargs, 'integrated_rom_size', 0x14000)
-        else:
             dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x10000)
 
         sys_clk_freq = int(100e6)

diff --git a/targets/mimas_a7/net.py b/targets/mimas_a7/net.py
@@ -3,6 +3,7 @@
 from liteeth.mac import LiteEthMAC
 from liteeth.phy.s7rgmii import LiteEthPHYRGMII
 
+from targets.utils import dict_set_max
 from .base import BaseSoC
 
 
@@ -12,6 +13,9 @@ class NetSoC(BaseSoC):
     }}
 
     def __init__(self, platform, *args, **kwargs):
+        # Need a larger integrated ROM to fit the BIOS with TFTP support.
+        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+
         BaseSoC.__init__(self, platform, *args, **kwargs)
 
         # Ethernet ---------------------------------------------------------------------------------

diff --git a/targets/mimasv2/base.py b/targets/mimasv2/base.py
@@ -100,9 +100,9 @@ def __init__(self, platform, **kwargs):
             platform.spiflash_total_size)
 
         if kwargs.get('cpu_type', None) == "mor1kx":
-            bios_size = 0x14000
-        else:
             bios_size = 0x10000
+        else:
+            bios_size = 0x8000
 
         self.add_constant("ROM_DISABLE", 1)
         self.add_memory_region(

diff --git a/targets/minispartan6/base.py b/targets/minispartan6/base.py
@@ -81,7 +81,11 @@ def __init__(self, platform, **kwargs):
             self.mem_map["spiflash"],
             platform.spiflash_total_size)
 
-        bios_size = 0x10000
+        if kwargs.get('cpu_type', None) == "mor1kx":
+            bios_size = 0x10000
+        else:
+            bios_size = 0x8000
+
         self.add_constant("ROM_DISABLE", 1)
         self.add_memory_region(
             "rom", kwargs['cpu_reset_address'], bios_size,

diff --git a/targets/neso/base.py b/targets/neso/base.py
@@ -89,7 +89,10 @@ class BaseSoC(SoCSDRAM):
     }}
 
     def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
-        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        if kwargs.get('cpu_type', None) == 'mor1kx':
+            dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
 
         clk_freq = int(100e6)

diff --git a/targets/netv2/base.py b/targets/netv2/base.py
@@ -102,7 +102,10 @@ class BaseSoC(SoCSDRAM):
     }}
 
     def __init__(self, platform, csr_data_width=8, **kwargs):
-        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        if kwargs.get('cpu_type', None) == 'mor1kx':
+            dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
 
         clk_freq = int(100e6)

diff --git a/targets/netv2/net.py b/targets/netv2/net.py
@@ -14,6 +14,9 @@ class NetSoC(BaseSoC):
     }}
 
     def __init__(self, platform, *args, **kwargs):
+        # Need a larger integrated ROM to fit the BIOS with TFTP support.
+        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+
         BaseSoC.__init__(self, platform, *args, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRMII(

diff --git a/targets/nexys_video/base.py b/targets/nexys_video/base.py
@@ -28,7 +28,10 @@ class BaseSoC(SoCSDRAM):
     #    "uart_phy",
 
     def __init__(self, platform, spiflash="spiflash_1x", **kwargs):
-        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        if kwargs.get('cpu_type', None) == 'mor1kx':
+            dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
 
         sys_clk_freq = int(100e6)

diff --git a/targets/nexys_video/net.py b/targets/nexys_video/net.py
@@ -4,6 +4,7 @@
 from liteeth.mac import LiteEthMAC
 from liteeth.phy.s7rgmii import LiteEthPHYRGMII
 
+from targets.utils import dict_set_max
 from targets.nexys_video.base import SoC as BaseSoC
 
 
@@ -14,6 +15,9 @@ class NetSoC(BaseSoC):
     )
 
     def __init__(self, platform, *args, **kwargs):
+        # Need a larger integrated ROM to fit the BIOS with TFTP support.
+        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+
         BaseSoC.__init__(self, platform, *args, **kwargs)
 
         # Ethernet PHY

diff --git a/targets/opsis/base.py b/targets/opsis/base.py
@@ -58,9 +58,9 @@ class BaseSoC(SoCSDRAM):
 
     def __init__(self, platform, **kwargs):
         if kwargs.get('cpu_type', None) == "mor1kx":
-            dict_set_max(kwargs, 'integrated_rom_size', 0x15000)
-        else:
             dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
 
         sys_clk_freq = 50*1000000

diff --git a/targets/opsis/net.py b/targets/opsis/net.py
@@ -4,6 +4,7 @@
 
 from gateware.s6rgmii import LiteEthPHYRGMII
 
+from targets.utils import dict_set_max
 from .base import BaseSoC
 
 
@@ -13,6 +14,9 @@ class NetSoC(BaseSoC):
     }}
 
     def __init__(self, platform, *args, **kwargs):
+        # Need a larger integrated ROM to fit the BIOS with TFTP support.
+        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+
         BaseSoC.__init__(self, platform, *args, **kwargs)
 
         # Ethernet ---------------------------------------------------------------------------------

diff --git a/targets/pano_logic_g2/base.py b/targets/pano_logic_g2/base.py
@@ -23,7 +23,10 @@ class BaseSoC(SoCSDRAM):
     }}
 
     def __init__(self, platform, **kwargs):
-        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        if kwargs.get('cpu_type', None) == 'mor1kx':
+            dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
 
         sys_clk_freq = int(50e6)

diff --git a/targets/pipistrello/base.py b/targets/pipistrello/base.py
@@ -27,9 +27,9 @@ class BaseSoC(SoCSDRAM):
 
     def __init__(self, platform, **kwargs):
         if kwargs.get('cpu_type', None) == "mor1kx":
-            dict_set_max(kwargs, 'integrated_rom_size', 0x14000)
-        else:
             dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x4000)
 
         sys_clk_freq = (83 + Fraction(1, 3))*1000*1000

diff --git a/targets/saturn/base.py b/targets/saturn/base.py
@@ -26,7 +26,10 @@ class BaseSoC(SoCSDRAM):
     }}
 
     def __init__(self, platform, **kwargs):
-        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        if kwargs.get('cpu_type', None) == 'mor1kx':
+            dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x4000)
 
         sys_clk_freq = (31 + Fraction(1, 4))*1000*1000

diff --git a/targets/sim/base.py b/targets/sim/base.py
@@ -23,6 +23,10 @@ class BaseSoC(SoCSDRAM):
 
     def __init__(self, platform, **kwargs):
         dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        if kwargs.get('cpu_type', None) == 'mor1kx':
+            dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
         dict_set_max(kwargs, 'firmware_ram_size', 0x10000)
 

diff --git a/targets/sim/net.py b/targets/sim/net.py
@@ -3,6 +3,7 @@
 from liteeth.phy.model import LiteEthPHYModel
 from liteeth.core.mac import LiteEthMAC
 
+from targets.utils import dict_set_max
 from targets.sim.base import BaseSoC
 
 
@@ -12,6 +13,9 @@ class NetSoC(BaseSoC):
     }}
 
     def __init__(self, *args, **kwargs):
+        # Need a larger integrated ROM to fit the BIOS with TFTP support.
+        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+
         BaseSoC.__init__(self, *args, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))

diff --git a/targets/waxwing/base.py b/targets/waxwing/base.py
@@ -27,7 +27,10 @@ class BaseSoC(SoCSDRAM):
     }}
 
     def __init__(self, platform, **kwargs):
-        dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        if kwargs.get('cpu_type', None) == 'mor1kx':
+            dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
+        else:
+            dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
         dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
 
         sys_clk_freq = (31 + Fraction(1, 4))*1000*1000

diff --git a/targets/waxwing/net.py b/targets/waxwing/net.py
@@ -31,8 +31,8 @@
 
 class BaseSoC(SoCSDRAM):
     def __init__(self, platform, **kwargs):
+        # Need a larger integrated ROM to fit the BIOS with TFTP support.
         dict_set_max(kwargs, 'integrated_rom_size', 0x10000)
-        dict_set_max(kwargs, 'integrated_sram_size', 0x8000)
 
         clk_freq = (31 + Fraction(1, 4))*1000*1000
         SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)