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Bumps yosys from
dce037a
to10bcc4e
.Commits
10bcc4e
Bump versionec2a468
backend/verilog: Add alternate mode for transparent read port output.4451f7f
memory_bram: Some refactoring12db9b4
Bump versionc4a295c
Update version.ymlcfddef5
Fixes xc7 BRAM36sc016f6a
proc_rmdead: use explicit pattern set when there are no wildcards4fec3a8
genrtlil: add width detection for AST_PREFIX nodes87ef1dd
Bump version54e7512
opt_lut: Allow more than one -dlogic per cell type.Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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