Implement SIMD comparison operations for types with less than 4 lanes (i128) #1146
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## master #1146 +/- ##
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- Coverage 82.55% 82.55% -0.01%
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Files 169 169
Lines 50456 50456
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- Hits 41655 41653 -2
- Misses 8801 8803 +2
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Co-authored-by: Paddy Horan <5733408+paddyhoran@users.noreply.github.com>
Co-authored-by: Paddy Horan <5733408+paddyhoran@users.noreply.github.com>
alamb
reviewed
Jan 10, 2022
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| // Fails when simd is enabled: https://github.com/apache/arrow-rs/issues/1136 | |||
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Thanks @jhorstmann fyi @tustvold |
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Which issue does this PR close?
Implements comparison for simd types with less than 8 lanes.
Closes #1136 .
What changes are included in this PR?
This PR changes the comparison kernel so that the simd portion can always append 64 bits at a time. Since the simd types are 512 bits wide, this means the inner comparison is unrolled, for example 8 times for Float64 (8 x 8lanes) or 4 times for Float32 (4 x 16lanes). For Int8 types it does not get unrolled since one comparison already results in 64 bits.
This should even speed up the comparison kernel a bit for common types, because there is less loop overhead.
On my laptop the simd version for
i128MonthDayNanotypes is not actually faster than the scalar version, on a more modern or server class machine there should be a slight speedup.Unrelated to this change I also noticed that the code generation for non-avx512 machines is sub-optimal since the compiler has to emulate the 512bit wider operations using smaller vector registers, and for the bitmap generating code this has some overhead.
Are there any user-facing changes?