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[DEPRECATION] Cleanup legacy verilog support (#4576)
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This PR cleans up the left over code for legacy verilog support which was experimental.
The new hardware backend path is now support by VTA via TSIM.
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tqchen authored Dec 24, 2019
1 parent c90160b commit ff65698
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5 changes: 0 additions & 5 deletions CMakeLists.txt
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Expand Up @@ -168,11 +168,6 @@ endif(USE_VM_PROFILER)
file(GLOB DATATYPE_SRCS src/codegen/datatype/*.cc)
list(APPEND COMPILER_SRCS ${DATATYPE_SRCS})

if(NOT MSVC)
file(GLOB COMPILER_VERILOG_SRCS src/codegen/verilog/*.cc)
list(APPEND COMPILER_SRCS ${COMPILER_VERILOG_SRCS})
endif()


file(GLOB TOPI_SRCS
topi/src/*.cc
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30 changes: 0 additions & 30 deletions docker/install/ubuntu_install_iverilog.sh

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73 changes: 0 additions & 73 deletions include/tvm/channel.h

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15 changes: 0 additions & 15 deletions include/tvm/ir_pass.h
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Expand Up @@ -236,21 +236,6 @@ bool VerifyCompactBuffer(Stmt stmt);
*/
Stmt RemoveNoOp(Stmt stmt);

/*!
* \brief Split statement into pipeine stages.
* \param stmt The stmt to be splitted
* \param split_load Whether split load into its own stage.
* \return Transformed stmt.
*/
Stmt SplitPipeline(Stmt stmt, bool split_load);

/*!
* \brief Narrow channel access to smaller range.
* \param stmt The stmt to do access rewriting.
* \return Transformed stmt.
*/
Stmt NarrowChannelAccess(Stmt stmt);

/*!
* \brief unroll the constant loop marked by unroll.
* This pass also automatically attach pragma unroll tag to loops which meets the standard.
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