[MetaSchedule][M4a] Schedule Rule: Multi-Level-Tiling #10043
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jinhongyii
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comaniac,
Hzfengsy,
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junrushao,
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merrymercy,
tqchen,
vinx13,
yzhliu,
zhiics and
ZihengJiang
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| - None on CPU | ||
| - [blockIdx.x, vthread.x, threadIdx.x] on GPU | ||
| use_tensor_core : bool | ||
| Whether to apply tensor core wmma intrinsic for the computation |
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This is probably a broader question, but are we going to bake tensorcore specific logic into this core schedule rule? What if I want to support other matrix cores from Intel or AMD?
I feel like the design should be that backend specific rules be decoupled from the main "driver" that does actual tiling like the one introduced in this PR. cc @junrushao1994 @vinx13
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Yes. We want to support auto tensorization for all hardware platforms. use-tensor-core is probably not a good name here - maybe use-tensor-intrin could be a better one
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I brought this up because I saw the upcoming code in https://github.com/junrushao1994/tvm/blob/meta-schedule/src/meta_schedule/schedule_rule/multi_level_tiling.cc where tensorcore stuff is hardcoded all over the place. I expect non-trivial refactoring before we can land this on main.
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Well, you are right. We might want to remove all the tensor core hard-coding here and focusing on AutoScheduler alignment first during upstreaming
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junrushao
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* multi level tiling * remove tensor core related code * pylint * fix Co-authored-by: Junru Shao <junrushao1994@gmail.com>
* multi level tiling * remove tensor core related code * pylint * fix Co-authored-by: Junru Shao <junrushao1994@gmail.com>
This PR is one of the schedule rule for MetaSchedule.
The rule does not support auto tensorization for now.
Co-authored-by: Junru Shao junrushao1994@gmail.com
Co-authored-by: Xiyou Zhou xiyou@octoml.ai
Co-authored-by: Bohan Hou spectrometerh@gmail.com
Co-authored-by: Siyuan Feng Hzfengsy@sjtu.edu.cn
Co-authored-by: Ruihang Lai lairuihangdongdong@qq.com
Co-authored-by: Wuwei Lin wuwei@apache.org
@junrushao1994 @Hzfengsy @comaniac