[Relay] Fix an assertion exposed by loop vectorizer #4916
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- Allows uniform conditions for select expressions (the same as halide) exposed by the loop vectorizer. Signed-off-by: Wei Pan <weip@nvidia.com>
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TVM and Halide are the same while vectorizing a select op: https://github.com/apache/incubator-tvm/blob/master/src/tir/pass/vectorize_loop.cc#L219 https://github.com/halide/Halide/blob/master/src/VectorizeLoops.cpp#L495 |
tqchen
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Feb 20, 2020
alexwong
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Feb 26, 2020
- Allows uniform conditions for select expressions (the same as halide) exposed by the loop vectorizer. Signed-off-by: Wei Pan <weip@nvidia.com>
alexwong
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Feb 28, 2020
- Allows uniform conditions for select expressions (the same as halide) exposed by the loop vectorizer. Signed-off-by: Wei Pan <weip@nvidia.com>
zhiics
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Mar 2, 2020
- Allows uniform conditions for select expressions (the same as halide) exposed by the loop vectorizer. Signed-off-by: Wei Pan <weip@nvidia.com>
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exposed by the loop vectorizer.
Signed-off-by: Wei Pan weip@nvidia.com
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