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[CUDA] Parallel Cuda Mergesort #7099
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f6488d5
implement parallel cuda mergesort
2a50289
fix a bug in build module when optimizing the host section of mixed h…
1817989
convert loop indices to int64 to prevent overflow in start calculation
dcf18e1
comments and cleanup
84a2e2d
fix lint
2d6d516
fix python casing
5bc7a41
enable more flaky tests
1cbbb8f
fix lint
e0b8994
fix lint, really enable test
7a53180
fix bad rebase
7abb3a0
fix lint
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For the record, segfault with nvptx was happening because the generated host code was calling intrinsics registered for nvptx, like
__nv_log2
or__nv_ceil
. The reason it was working on CUDA was just by coincident: there is no CUDA intrinsics registered for fp64 log2, ceil, so TVM was using the default lowering, which happens to be the right one (llvm).This change fixes that issue.