SAMD21G18A TCC3 Timer Support

[davidcutting42]

I've been trying to use TCC3 on the SAMD21 in a project, but there is not support for it in Arduino. It looks like Atmel/Microchip added TCC3 in a later silicon revision. Is there any way I could get these built?

I'm willing to do it myself, but I'm afraid I don't have the know-how.

[daHuaba]

You find everything you need in the datasheet, I just started by creating tcc3.h from tcc0.h (as it has the same specs) for my own hackaround:

/**
 * \file
 *
 * \brief Instance description for TCC3
 *
 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
 *
 * \asf_license_start
 *
 * \page License
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * 3. The name of Atmel may not be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * 4. This software may only be redistributed and used in connection with an
 *    Atmel microcontroller product.
 *
 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * \asf_license_stop
 *
 */

#ifndef _SAMD21_TCC3_INSTANCE_
#define _SAMD21_TCC3_INSTANCE_

/* ========== Register definition for TCC3 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TCC3_CTRLA             (0x42006000U) /**< \brief (TCC3) Control A */
#define REG_TCC3_CTRLBCLR          (0x42006004U) /**< \brief (TCC3) Control B Clear */
#define REG_TCC3_CTRLBSET          (0x42006005U) /**< \brief (TCC3) Control B Set */
#define REG_TCC3_SYNCBUSY          (0x42006008U) /**< \brief (TCC3) Synchronization Busy */
#define REG_TCC3_FCTRLA            (0x4200600CU) /**< \brief (TCC3) Recoverable Fault A Configuration */
#define REG_TCC3_FCTRLB            (0x42006010U) /**< \brief (TCC3) Recoverable Fault B Configuration */
#define REG_TCC3_WEXCTRL           (0x42006014U) /**< \brief (TCC3) Waveform Extension Configuration */
#define REG_TCC3_DRVCTRL           (0x42006018U) /**< \brief (TCC3) Driver Control */
#define REG_TCC3_DBGCTRL           (0x4200601EU) /**< \brief (TCC3) Debug Control */
#define REG_TCC3_EVCTRL            (0x42006020U) /**< \brief (TCC3) Event Control */
#define REG_TCC3_INTENCLR          (0x42006024U) /**< \brief (TCC3) Interrupt Enable Clear */
#define REG_TCC3_INTENSET          (0x42006028U) /**< \brief (TCC3) Interrupt Enable Set */
#define REG_TCC3_INTFLAG           (0x4200602CU) /**< \brief (TCC3) Interrupt Flag Status and Clear */
#define REG_TCC3_STATUS            (0x42006030U) /**< \brief (TCC3) Status */
#define REG_TCC3_COUNT             (0x42006034U) /**< \brief (TCC3) Count */
#define REG_TCC3_PATT              (0x42006038U) /**< \brief (TCC3) Pattern */
#define REG_TCC3_WAVE              (0x4200603CU) /**< \brief (TCC3) Waveform Control */
#define REG_TCC3_PER               (0x42006040U) /**< \brief (TCC3) Period */
#define REG_TCC3_CC0               (0x42006044U) /**< \brief (TCC3) Compare and Capture 0 */
#define REG_TCC3_CC1               (0x42006048U) /**< \brief (TCC3) Compare and Capture 1 */
#define REG_TCC3_CC2               (0x4200604CU) /**< \brief (TCC3) Compare and Capture 2 */
#define REG_TCC3_CC3               (0x42006050U) /**< \brief (TCC3) Compare and Capture 3 */
#define REG_TCC3_PATTB             (0x42006064U) /**< \brief (TCC3) Pattern Buffer */
#define REG_TCC3_WAVEB             (0x42006068U) /**< \brief (TCC3) Waveform Control Buffer */
#define REG_TCC3_PERB              (0x4200606CU) /**< \brief (TCC3) Period Buffer */
#define REG_TCC3_CCB0              (0x42006070U) /**< \brief (TCC3) Compare and Capture Buffer 0 */
#define REG_TCC3_CCB1              (0x42006074U) /**< \brief (TCC3) Compare and Capture Buffer 1 */
#define REG_TCC3_CCB2              (0x42006078U) /**< \brief (TCC3) Compare and Capture Buffer 2 */
#define REG_TCC3_CCB3              (0x4200607CU) /**< \brief (TCC3) Compare and Capture Buffer 3 */
#else
#define REG_TCC3_CTRLA             (*(RwReg  *)0x42006000U) /**< \brief (TCC3) Control A */
#define REG_TCC3_CTRLBCLR          (*(RwReg8 *)0x42006004U) /**< \brief (TCC3) Control B Clear */
#define REG_TCC3_CTRLBSET          (*(RwReg8 *)0x42006005U) /**< \brief (TCC3) Control B Set */
#define REG_TCC3_SYNCBUSY          (*(RoReg  *)0x42006008U) /**< \brief (TCC3) Synchronization Busy */
#define REG_TCC3_FCTRLA            (*(RwReg  *)0x4200600CU) /**< \brief (TCC3) Recoverable Fault A Configuration */
#define REG_TCC3_FCTRLB            (*(RwReg  *)0x42006010U) /**< \brief (TCC3) Recoverable Fault B Configuration */
#define REG_TCC3_WEXCTRL           (*(RwReg  *)0x42006014U) /**< \brief (TCC3) Waveform Extension Configuration */
#define REG_TCC3_DRVCTRL           (*(RwReg  *)0x42006018U) /**< \brief (TCC3) Driver Control */
#define REG_TCC3_DBGCTRL           (*(RwReg8 *)0x4200601EU) /**< \brief (TCC3) Debug Control */
#define REG_TCC3_EVCTRL            (*(RwReg  *)0x42006020U) /**< \brief (TCC3) Event Control */
#define REG_TCC3_INTENCLR          (*(RwReg  *)0x42006024U) /**< \brief (TCC3) Interrupt Enable Clear */
#define REG_TCC3_INTENSET          (*(RwReg  *)0x42006028U) /**< \brief (TCC3) Interrupt Enable Set */
#define REG_TCC3_INTFLAG           (*(RwReg  *)0x4200602CU) /**< \brief (TCC3) Interrupt Flag Status and Clear */
#define REG_TCC3_STATUS            (*(RwReg  *)0x42006030U) /**< \brief (TCC3) Status */
#define REG_TCC3_COUNT             (*(RwReg  *)0x42006034U) /**< \brief (TCC3) Count */
#define REG_TCC3_PATT              (*(RwReg16*)0x42006038U) /**< \brief (TCC3) Pattern */
#define REG_TCC3_WAVE              (*(RwReg  *)0x4200603CU) /**< \brief (TCC3) Waveform Control */
#define REG_TCC3_PER               (*(RwReg  *)0x42006040U) /**< \brief (TCC3) Period */
#define REG_TCC3_CC0               (*(RwReg  *)0x42006044U) /**< \brief (TCC3) Compare and Capture 0 */
#define REG_TCC3_CC1               (*(RwReg  *)0x42006048U) /**< \brief (TCC3) Compare and Capture 1 */
#define REG_TCC3_CC2               (*(RwReg  *)0x4200604CU) /**< \brief (TCC3) Compare and Capture 2 */
#define REG_TCC3_CC3               (*(RwReg  *)0x42006050U) /**< \brief (TCC3) Compare and Capture 3 */
#define REG_TCC3_PATTB             (*(RwReg16*)0x42006064U) /**< \brief (TCC3) Pattern Buffer */
#define REG_TCC3_WAVEB             (*(RwReg  *)0x42006068U) /**< \brief (TCC3) Waveform Control Buffer */
#define REG_TCC3_PERB              (*(RwReg  *)0x4200606CU) /**< \brief (TCC3) Period Buffer */
#define REG_TCC3_CCB0              (*(RwReg  *)0x42006070U) /**< \brief (TCC3) Compare and Capture Buffer 0 */
#define REG_TCC3_CCB1              (*(RwReg  *)0x42006074U) /**< \brief (TCC3) Compare and Capture Buffer 1 */
#define REG_TCC3_CCB2              (*(RwReg  *)0x42006078U) /**< \brief (TCC3) Compare and Capture Buffer 2 */
#define REG_TCC3_CCB3              (*(RwReg  *)0x4200607CU) /**< \brief (TCC3) Compare and Capture Buffer 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* ========== Instance parameters for TCC3 peripheral ========== */
#define TCC3_CC_NUM                 4        // Number of Compare/Capture units
#define TCC3_DITHERING              1        // Dithering feature implemented
#define TCC3_DMAC_ID_MC_0           0x2E
#define TCC3_DMAC_ID_MC_1           0x2F
#define TCC3_DMAC_ID_MC_2           0x30
#define TCC3_DMAC_ID_MC_3           0x31
#define TCC3_DMAC_ID_MC_LSB         0x2E
#define TCC3_DMAC_ID_MC_MSB         0x31
#define TCC3_DMAC_ID_MC_SIZE        4
#define TCC3_DMAC_ID_OVF            0x2D       // DMA overflow/underflow/retrigger trigger
#define TCC3_DTI                    1        // Dead-Time-Insertion feature implemented
#define TCC3_EXT                    31       // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
#define TCC3_GCLK_ID                37       // Index of Generic Clock
#define TCC3_OTMX                   1        // Output Matrix feature implemented
#define TCC3_OW_NUM                 8        // Number of Output Waveforms
#define TCC3_PG                     1        // Pattern Generation feature implemented
#define TCC3_SIZE                   24      
#define TCC3_SWAP                   1        // DTI outputs swap feature implemented
#define TCC3_TYPE                   0        // TCC type 0 : NA, 1 : Master, 2 : Slave

#endif /* _SAMD21_TCC3_INSTANCE_ */

[daHuaba]

Next, I added the following line 311 in samd21g18a.h (as I'm using this particular processor):

#include "instance/tcc3.h"

and line 411

#define TCC3 (0x42006000UL) /**< \brief (TCC3) APB Base Address */

and finally line 515:

#define TCC3 ((Tcc *)0x42006000UL) /**< \brief (TCC3) APB Base Address */

Edit: If I make some mistakes on the way, feel free to tell me before I find out later.

Additionally, I added line 120:

TCC3_IRQn = 29, /**< 29 SAMD21G18A Timer Counter Control 3 (TCC3) */

and line 214:

void TCC3_Handler ( void );

Not to forget line 185 (after the reserved position 28):

void* pfnTCC3_Handler; /* 29 Timer Counter Control 3 */

and changing lines 519 and 520:

#define TCC_INST_NUM      4                          /**< \brief (TCC) Number of instances */
#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */

Edit: Found one more position to change, lines 364-366:

#define ID_TCC3          85 /**< \brief Timer Counter Control 3 (TCC3) */

#define ID_PERIPH_COUNT  86 /**< \brief Max number of peripheral IDs */

[daHuaba]

Next, I added in file evsys.h (instance) line 165:

#define EVSYS_ID_GEN_AC_COMP_2      74
#define EVSYS_ID_GEN_AC_COMP_3      75
#define EVSYS_ID_GEN_AC_WIN_1       76
#define EVSYS_ID_GEN_TCC3_OVF       77
#define EVSYS_ID_GEN_TCC3_TRG       78
#define EVSYS_ID_GEN_TCC3_CNT       79
#define EVSYS_ID_GEN_TCC3_MCX_0     80
#define EVSYS_ID_GEN_TCC3_MCX_1     81
#define EVSYS_ID_GEN_TCC3_MCX_2     82
#define EVSYS_ID_GEN_TCC3_MCX_3     83

and in line 206:

#define EVSYS_ID_USER_AC_SOC_2      29
#define EVSYS_ID_USER_AC_SOC_3      30
#define EVSYS_ID_USER_TCC3_EV_0     31
#define EVSYS_ID_USER_TCC3_EV_1     32
#define EVSYS_ID_USER_TCC3_MC_0     33
#define EVSYS_ID_USER_TCC3_MC_1     34
#define EVSYS_ID_USER_TCC3_MC_2     35
#define EVSYS_ID_USER_TCC3_MC_3     36

[daHuaba]

Next file to change was samd21g18a (pio) by adding the following lines:

/* ========== PORT definition for TCC3 peripheral ========== */
#DEFINE PIN_PA02F_TCC3_WO0                 2L  /**< \brief TCC3 signal: WO0 on PA02 mux F */
#DEFINE MUX_PA02F_TCC3_WO0                 5L
#DEFINE PINMUX_PA02F_TCC3_WO0      ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
#DEFINE PORT_PA02F_TCC3_WO0        (1ul << 2)
#DEFINE PIN_PA03F_TCC3_WO1                 3L  /**< \brief TCC3 signal: WO1 on PA03 mux F */
#DEFINE MUX_PA03F_TCC3_WO1                 5L
#DEFINE PINMUX_PA03F_TCC3_WO1      ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
#DEFINE PORT_PA03F_TCC3_WO1        (1ul << 3)
#DEFINE PIN_PB08F_TCC3_WO6                 8L  /**< \brief TCC3 signal: WO6 on PB08 mux F */
#DEFINE MUX_PB08F_TCC3_WO6                 5L
#DEFINE PINMUX_PB08F_TCC3_WO6      ((PIN_PB08F_TCC3_WO6 << 16) | MUX_PB08F_TCC3_WO6)
#DEFINE PORT_PB08F_TCC3_WO6        (1ul << 8)
#DEFINE PIN_PB09F_TCC3_WO7                 9L  /**< \brief TCC3 signal: WO7 on PB09 mux F */
#DEFINE MUX_PB09F_TCC3_WO7                 5L
#DEFINE PINMUX_PB09F_TCC3_WO7      ((PIN_PB09F_TCC3_WO7 << 16) | MUX_PB09F_TCC3_WO7)
#DEFINE PORT_PB09F_TCC3_WO7        (1ul << 9)
#DEFINE PIN_PA04F_TCC3_WO2                 4L  /**< \brief TCC3 signal: WO2 on PA04 mux F */
#DEFINE MUX_PA04F_TCC3_WO2                 5L
#DEFINE PINMUX_PA04F_TCC3_WO2      ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
#DEFINE PORT_PA04F_TCC3_WO2        (1ul << 4)
#DEFINE PIN_PA05F_TCC3_WO3                 5L  /**< \brief TCC3 signal: WO3 on PA05 mux F */
#DEFINE MUX_PA05F_TCC3_WO3                 5L
#DEFINE PINMUX_PA05F_TCC3_WO3      ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
#DEFINE PORT_PA05F_TCC3_WO3        (1ul << 5)
#DEFINE PIN_PA06F_TCC3_WO4                 6L  /**< \brief TCC3 signal: WO4 on PA06 mux F */
#DEFINE MUX_PA06F_TCC3_WO4                 5L
#DEFINE PINMUX_PA06F_TCC3_WO4      ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
#DEFINE PORT_PA06F_TCC3_WO4        (1ul << 6)
#DEFINE PIN_PA07F_TCC3_WO5                 7L  /**< \brief TCC3 signal: WO5 on PA07 mux F */
#DEFINE MUX_PA07F_TCC3_WO5                 5L
#DEFINE PINMUX_PA07F_TCC3_WO5      ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
#DEFINE PORT_PA07F_TCC3_WO5        (1ul << 7)
#DEFINE PIN_PB22F_TCC3_WO0                 22L  /**< \brief TCC3 signal: WO0 on PB22 mux F */
#DEFINE MUX_PB22F_TCC3_WO0                 5L
#DEFINE PINMUX_PB22F_TCC3_WO0      ((PIN_PB22F_TCC3_WO0 << 16) | MUX_PB22F_TCC3_WO0)
#DEFINE PORT_PB22F_TCC3_WO0        (1ul << 22)
#DEFINE PIN_PB23F_TCC3_WO1                 23L  /**< \brief TCC3 signal: WO1 on PB23 mux F */
#DEFINE MUX_PB23F_TCC3_WO1                 5L
#DEFINE PINMUX_PB23F_TCC3_WO1      ((PIN_PB23F_TCC3_WO1 << 16) | MUX_PB23F_TCC3_WO1)
#DEFINE PORT_PB23F_TCC3_WO1        (1ul << 23)
#DEFINE PIN_PA27F_TCC3_WO6                 27L  /**< \brief TCC3 signal: WO6 on PA27 mux F */
#DEFINE MUX_PA27F_TCC3_WO6                 5L
#DEFINE PINMUX_PA27F_TCC3_WO6      ((PIN_PA27F_TCC3_WO6 << 16) | MUX_PA27F_TCC3_WO6)
#DEFINE PORT_PA27F_TCC3_WO6        (1ul << 27)
#DEFINE PIN_PA28F_TCC3_WO7                 28L  /**< \brief TCC3 signal: WO7 on PA28 mux F */
#DEFINE MUX_PA28F_TCC3_WO7                 5L
#DEFINE PINMUX_PA28F_TCC3_WO7      ((PIN_PA28F_TCC3_WO7 << 16) | MUX_PA28F_TCC3_WO7)
#DEFINE PORT_PA28F_TCC3_WO7        (1ul << 28)
#DEFINE PIN_PA30F_TCC3_WO4                 30L  /**< \brief TCC3 signal: WO4 on PA30 mux F */
#DEFINE MUX_PA30F_TCC3_WO4                 5L
#DEFINE PINMUX_PA30F_TCC3_WO4      ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
#DEFINE PORT_PA30F_TCC3_WO4        (1ul << 30)
#DEFINE PIN_PA31F_TCC3_WO5                 31L  /**< \brief TCC3 signal: WO5 on PA31 mux F */
#DEFINE MUX_PA31F_TCC3_WO5                 5L
#DEFINE PINMUX_PA31F_TCC3_WO5      ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
#DEFINE PORT_PA31F_TCC3_WO5        (1ul << 31)
#DEFINE PIN_PB02F_TCC3_WO2                 2L  /**< \brief TCC3 signal: WO2 on PB02 mux F */
#DEFINE MUX_PB02F_TCC3_WO2                 5L
#DEFINE PINMUX_PB02F_TCC3_WO2      ((PIN_PB02F_TCC3_WO2 << 16) | MUX_PB02F_TCC3_WO2)
#DEFINE PORT_PB02F_TCC3_WO2        (1ul << 2)
#DEFINE PIN_PB03F_TCC3_WO3                 3L  /**< \brief TCC3 signal: WO3 on PB03 mux F */
#DEFINE MUX_PB03F_TCC3_WO3                 5L
#DEFINE PINMUX_PB03F_TCC3_WO3      ((PIN_PB03F_TCC3_WO3 << 16) | MUX_PB03F_TCC3_WO3)
#DEFINE PORT_PB03F_TCC3_WO3        (1ul << 3)

[daHuaba]

In the Power Manager (pm.h, component) I changed line 366:

    uint32_t AC1_:1;           /*!< bit:     21  AC1 APB Clock Enable               */
    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
	uint32_t TCC3_:1;          /*!< bit:     24  TCC3 APB Clock Enable              */
    uint32_t :7;               /*!< bit: 25..31  Reserved                           */

and added in line 420:

#define PM_APBCMASK_AC1_Pos         21           /**< \brief (PM_APBCMASK) AC1 APB Clock Enable */
#define PM_APBCMASK_AC1             (0x1ul << PM_APBCMASK_AC1_Pos)
#define PM_APBCMASK_TCC3_Pos        24           /**< \brief (PM_APBCMASK) TCC3 APB Clock Enable */
#define PM_APBCMASK_TCC3            (0x1ul << PM_APBCMASK_TCC3_Pos)

[daHuaba]

Finally I added in gclk.h (component) in line 150:
#define GCLK_CLKCTRL_ID_TCC3_Val 0x25ul /**< \brief (GCLK_CLKCTRL) TCC3 */

and in line 188:

#define GCLK_CLKCTRL_ID_TCC3 (GCLK_CLKCTRL_ID_TCC3_Val << GCLK_CLKCTRL_ID_Pos)

[daHuaba]

So here is my (untested) Code, can someone with more knowledge than me plz check and test it accordingly?

CMSIS.zip

Edit: in the pio-file #DEFINE has of course to be replaced with #define (lower case). Uploaded corrected Code.

[JAHTKELD]

Hello:
You have tried TCC3 in this way, does it work? I would need the TCC3 on the ATSAMD21G18A but I think it is only available on the ATSAMD21X17D according to Configuration Summary
Table 2-1 in the datasheet, since it is the only one that has 4 TCC (TTC0, TCC1, TCC2 and TCC3)

[daHuaba]

Hey, I'm getting an PWM Output from the pins, so either I have coded something else wrong or this is working. I can't tell for sure, as I do not see myself qualified enough to test it thoroughly.
Also, table 7-1 states TCC3 for SAMD21E, SAMD21G and SAMD21J devices.
If you have time to test it, I'd be happy to receive feedback.

[rburget]

Hey, there is a bad news based on the DS40001882F datasheet for SAM D21/DA1 Family,
"Table 2-1. SAM D21 E/G/J and SAM D21 EL/GL Product Family Features" shows the only device groups support 4 TCC are ATSAMD21x17D or ATSAMD21x17L.
ATSAMD21G18A supports 3 only, 0-3. I spent couple of days to try to make it work, but I wasn't able to turn on the clock REG_PM_APBCMASK for TCC3.

[daHuaba]

Hey, there is a bad news based on the DS40001882F datasheet for SAM D21/DA1 Family,
"Table 2-1. SAM D21 E/G/J and SAM D21 EL/GL Product Family Features" shows the only device groups support 4 TCC are ATSAMD21x17D or ATSAMD21x17L.
ATSAMD21G18A supports 3 only, 0-3. I spent couple of days to try to make it work, but I wasn't able to turn on the clock REG_PM_APBCMASK for TCC3.

Ok, thx for testing; I must have done something else wrong then to get a PWM-like output there. Probably the addressing makes the Pins turn on and off by accident when accessing the power manager or something.
I think you can close the issue then.