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# This is the 1st commit message:

chore: clippy

# The commit message #2 will be skipped:

# fixup! feat: exit code (#750)

# The commit message #3 will be skipped:

# fixup! feat: exit code (#750)

# The commit message #4 will be skipped:

# fixup! feat: exit code (#750)

# The commit message #5 will be skipped:

# fixup! feat: exit code (#750)
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huitseeker committed Jun 13, 2024
1 parent f9624d3 commit 1f9909f
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Showing 49 changed files with 203 additions and 237 deletions.
30 changes: 4 additions & 26 deletions Cargo.lock

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1 change: 1 addition & 0 deletions Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@ members = [
"zkvm/*",
]
exclude = ["examples/target"]
resolver = "2"

[profile.release]
opt-level = 3
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2 changes: 1 addition & 1 deletion core/src/alu/bitwise/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,7 @@ impl<F: PrimeField> MachineAir<F> for BitwiseChip {
shard: event.shard,
channel: event.channel,
opcode: ByteOpcode::try_from(event.opcode).unwrap(),
a1: b_a as u32,
a1: u32::from(b_a),
a2: 0,
b: u32::from(b_b),
c: u32::from(b_c),
Expand Down
2 changes: 1 addition & 1 deletion core/src/alu/divrem/utils.rs
Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ pub(crate) fn get_quotient_and_remainder(b: u32, c: u32, opcode: Opcode) -> (u32
}

/// Calculate the most significant bit of the given 32-bit integer `a`, and returns it as a u8.
pub const fn get_msb(a: u32) -> u8 {
pub(crate) const fn get_msb(a: u32) -> u8 {
((a >> 31) & 1) as u8
}

Expand Down
2 changes: 1 addition & 1 deletion core/src/alu/mul/utils.rs
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
use super::BYTE_SIZE;
use crate::air::WORD_SIZE;

pub const fn get_msb(a: [u8; WORD_SIZE]) -> u8 {
pub(crate) const fn get_msb(a: [u8; WORD_SIZE]) -> u8 {
(a[WORD_SIZE - 1] >> (BYTE_SIZE - 1)) & 1
}
2 changes: 1 addition & 1 deletion core/src/alu/sll/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -386,7 +386,7 @@ mod tests {
fn generate_trace() {
let mut shard = ExecutionRecord::default();
shard.shift_left_events = vec![AluEvent::new(0, 0, 0, Opcode::SLL, 16, 8, 1)];
let chip = ShiftLeft::default();
let chip = ShiftLeft;
let trace: RowMajorMatrix<BabyBear> =
chip.generate_trace(&shard, &mut ExecutionRecord::default());
println!("{:?}", trace.values)
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2 changes: 1 addition & 1 deletion core/src/alu/sr/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -526,7 +526,7 @@ mod tests {
fn generate_trace() {
let mut shard = ExecutionRecord::default();
shard.shift_right_events = vec![AluEvent::new(0, 0, 0, Opcode::SRL, 6, 12, 1)];
let chip = ShiftRightChip::default();
let chip = ShiftRightChip;
let trace: RowMajorMatrix<BabyBear> =
chip.generate_trace(&shard, &mut ExecutionRecord::default());
println!("{:?}", trace.values)
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4 changes: 2 additions & 2 deletions core/src/alu/sr/utils.rs
Original file line number Diff line number Diff line change
Expand Up @@ -3,15 +3,15 @@ use super::BYTE_SIZE;
/// Calculate the number of bytes to shift by.
///
/// Note that we take the least significant 5 bits per the RISC-V spec.
pub const fn nb_bytes_to_shift(shift_amount: u32) -> usize {
pub(crate) const fn nb_bytes_to_shift(shift_amount: u32) -> usize {
let n = (shift_amount % 32) as usize;
n / BYTE_SIZE
}

/// Calculate the number of bits shift by.
///
/// Note that we take the least significant 5 bits per the RISC-V spec.
pub const fn nb_bits_to_shift(shift_amount: u32) -> usize {
pub(crate) const fn nb_bits_to_shift(shift_amount: u32) -> usize {
let n = (shift_amount % 32) as usize;
n % BYTE_SIZE
}
70 changes: 56 additions & 14 deletions core/src/bytes/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -73,33 +73,63 @@ impl<F: Field> ByteChip<F> {
let and = b & c;
col.and = F::from_canonical_u8(and);
ByteLookupEvent::new(
shard, channel, *opcode, and as u32, 0, b as u32, c as u32,
shard,
channel,
*opcode,
u32::from(and),
0,
u32::from(b),
u32::from(c),
)
}
ByteOpcode::OR => {
let or = b | c;
col.or = F::from_canonical_u8(or);
ByteLookupEvent::new(
shard, channel, *opcode, or as u32, 0, b as u32, c as u32,
shard,
channel,
*opcode,
u32::from(or),
0,
u32::from(b),
u32::from(c),
)
}
ByteOpcode::XOR => {
let xor = b ^ c;
col.xor = F::from_canonical_u8(xor);
ByteLookupEvent::new(
shard, channel, *opcode, xor as u32, 0, b as u32, c as u32,
shard,
channel,
*opcode,
u32::from(xor),
0,
u32::from(b),
u32::from(c),
)
}
ByteOpcode::SLL => {
let sll = b << (c & 7);
col.sll = F::from_canonical_u8(sll);
ByteLookupEvent::new(
shard, channel, *opcode, sll as u32, 0, b as u32, c as u32,
shard,
channel,
*opcode,
u32::from(sll),
0,
u32::from(b),
u32::from(c),
)
}
ByteOpcode::U8Range => {
ByteLookupEvent::new(shard, channel, *opcode, 0, 0, b as u32, c as u32)
}
ByteOpcode::U8Range => ByteLookupEvent::new(
shard,
channel,
*opcode,
0,
0,
u32::from(b),
u32::from(c),
),
ByteOpcode::ShrCarry => {
let (res, carry) = shr_carry(b, c);
col.shr = F::from_canonical_u8(res);
Expand All @@ -108,28 +138,40 @@ impl<F: Field> ByteChip<F> {
shard,
channel,
*opcode,
res as u32,
carry as u32,
b as u32,
c as u32,
u32::from(res),
u32::from(carry),
u32::from(b),
u32::from(c),
)
}
ByteOpcode::LTU => {
let ltu = b < c;
col.ltu = F::from_bool(ltu);
ByteLookupEvent::new(
shard, channel, *opcode, ltu as u32, 0, b as u32, c as u32,
shard,
channel,
*opcode,
u32::from(ltu),
0,
u32::from(b),
u32::from(c),
)
}
ByteOpcode::MSB => {
let msb = (b & 0b1000_0000) != 0;
col.msb = F::from_bool(msb);
ByteLookupEvent::new(
shard, channel, *opcode, msb as u32, 0, b as u32, 0 as u32,
shard,
channel,
*opcode,
u32::from(msb),
0,
u32::from(b),
0_u32,
)
}
ByteOpcode::U16Range => {
let v = ((b as u32) << 8) + c as u32;
let v = (u32::from(b) << 8) + u32::from(c);
col.value_u16 = F::from_canonical_u32(v);
ByteLookupEvent::new(shard, channel, *opcode, v, 0, 0, 0)
}
Expand Down
2 changes: 1 addition & 1 deletion core/src/cpu/air/branch.rs
Original file line number Diff line number Diff line change
Expand Up @@ -174,7 +174,7 @@ impl CpuChip {
local.op_a_val(),
local.shard,
local.channel,
is_branch_instruction.clone(),
is_branch_instruction,
);
}
}
2 changes: 1 addition & 1 deletion core/src/cpu/air/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -76,7 +76,7 @@ where
&next.channel_selectors,
local.channel,
local.is_real,
next.is_real,
&next.is_real,
);

// ALU instructions.
Expand Down
8 changes: 3 additions & 5 deletions core/src/cpu/columns/channel.rs
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ pub fn eval_channel_selectors<AB: BaseAirBuilder>(
next: &ChannelSelectorCols<AB::Var>,
channel: impl Into<AB::Expr> + Clone,
local_is_real: impl Into<AB::Expr> + Clone,
next_is_real: impl Into<AB::Expr> + Clone,
next_is_real: &(impl Into<AB::Expr> + Clone),
) {
// Constrain:
// - the value of the channel is given by the channel selectors.
Expand All @@ -41,11 +41,9 @@ pub fn eval_channel_selectors<AB: BaseAirBuilder>(
reconstruct_channel += selector.into() * AB::Expr::from_canonical_u32(i as u32);
}
// Assert that the reconstructed channel is the same as the channel.
builder.assert_eq(reconstruct_channel, channel.clone());
builder.assert_eq(reconstruct_channel, channel);
// For disjointness, assert the sum of the selectors is 1.
builder
.when(local_is_real.clone())
.assert_eq(sum, AB::Expr::one());
builder.when(local_is_real).assert_eq(sum, AB::Expr::one());

// Constrain the first row by asserting that the first selector on the first line is true.
builder
Expand Down
2 changes: 1 addition & 1 deletion core/src/cpu/trace.rs
Original file line number Diff line number Diff line change
Expand Up @@ -354,7 +354,7 @@ impl CpuChip {
new_blu_events.push(ByteLookupEvent {
shard: event.shard,
channel: event.channel,
opcode: ByteOpcode::U8Range,
opcode: U8Range,
a1: 0,
a2: 0,
b: u32::from(byte_pair[0]),
Expand Down
2 changes: 1 addition & 1 deletion core/src/operations/add.rs
Original file line number Diff line number Diff line change
Expand Up @@ -105,7 +105,7 @@ impl<F: Field> AddOperation<F> {
{
builder.slice_range_check_u8(&a.0, shard, channel.clone(), is_real.clone());
builder.slice_range_check_u8(&b.0, shard, channel.clone(), is_real.clone());
builder.slice_range_check_u8(&cols.value.0, shard, channel.clone(), is_real);
builder.slice_range_check_u8(&cols.value.0, shard, channel, is_real);
}
}
}
4 changes: 2 additions & 2 deletions core/src/operations/field/field_den.rs
Original file line number Diff line number Diff line change
Expand Up @@ -150,7 +150,7 @@ impl<V: Copy, P: FieldParameters> FieldDenCols<V, P> {
channel.clone(),
is_real.clone(),
);
builder.slice_range_check_u8(&self.witness_high, shard, channel.clone(), is_real);
builder.slice_range_check_u8(&self.witness_high, shard, channel, is_real);
}
}

Expand Down Expand Up @@ -198,7 +198,7 @@ mod tests {
}

impl<P: FieldParameters> FieldDenChip<P> {
pub const fn new(sign: bool) -> Self {
pub(crate) const fn new(sign: bool) -> Self {
Self {
sign,
_phantom: std::marker::PhantomData,
Expand Down
4 changes: 2 additions & 2 deletions core/src/operations/field/field_inner_product.rs
Original file line number Diff line number Diff line change
Expand Up @@ -139,7 +139,7 @@ impl<V: Copy, P: FieldParameters> FieldInnerProductCols<V, P> {
channel.clone(),
is_real.clone(),
);
builder.slice_range_check_u8(&self.witness_high, shard, channel.clone(), is_real);
builder.slice_range_check_u8(&self.witness_high, shard, channel, is_real);
}
}

Expand Down Expand Up @@ -186,7 +186,7 @@ mod tests {
}

impl<P: FieldParameters> FieldIpChip<P> {
pub const fn new() -> Self {
pub(crate) const fn new() -> Self {
Self {
_phantom: std::marker::PhantomData,
}
Expand Down
13 changes: 5 additions & 8 deletions core/src/operations/field/field_op.rs
Original file line number Diff line number Diff line change
Expand Up @@ -240,12 +240,7 @@ impl<V: Copy, P: FieldParameters> FieldOpCols<V, P> {
channel.clone(),
is_real.clone(),
);
builder.slice_range_check_u8(
p_witness_high.coefficients(),
shard.clone(),
channel.clone(),
is_real,
);
builder.slice_range_check_u8(p_witness_high.coefficients(), shard, channel, is_real);
}

#[allow(clippy::too_many_arguments)]
Expand All @@ -261,7 +256,9 @@ impl<V: Copy, P: FieldParameters> FieldOpCols<V, P> {
) where
V: Into<AB::Expr>,
{
let p_limbs = Polynomial::from_iter(P::modulus_field_iter::<AB::F>().map(AB::Expr::from));
let p_limbs = P::modulus_field_iter::<AB::F>()
.map(AB::Expr::from)
.collect::<Polynomial<_>>();
self.eval_with_modulus::<AB>(builder, a, b, &p_limbs, op, shard, channel, is_real);
}
}
Expand Down Expand Up @@ -312,7 +309,7 @@ mod tests {
}

impl<P: FieldParameters> FieldOpChip<P> {
pub const fn new(operation: FieldOperation) -> Self {
pub(crate) const fn new(operation: FieldOperation) -> Self {
Self {
operation,
_phantom: std::marker::PhantomData,
Expand Down
2 changes: 1 addition & 1 deletion core/src/operations/field/field_sqrt.rs
Original file line number Diff line number Diff line change
Expand Up @@ -151,7 +151,7 @@ mod tests {
}

impl<P: FieldParameters> EdSqrtChip<P> {
pub const fn new() -> Self {
pub(crate) const fn new() -> Self {
Self {
_phantom: std::marker::PhantomData,
}
Expand Down
2 changes: 1 addition & 1 deletion core/src/operations/fixed_rotate_right.rs
Original file line number Diff line number Diff line change
Expand Up @@ -111,7 +111,7 @@ impl<F: Field> FixedRotateRightOperation<F> {
rotation: usize,
cols: FixedRotateRightOperation<AB::Var>,
shard: AB::Var,
channel: impl Into<AB::Expr> + Clone,
channel: &(impl Into<AB::Expr> + Clone),
is_real: AB::Var,
) {
// Compute some constants with respect to the rotation needed for the rotation.
Expand Down
2 changes: 1 addition & 1 deletion core/src/operations/xor.rs
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@ impl<F: Field> XorOperation<F> {
b: Word<AB::Var>,
cols: XorOperation<AB::Var>,
shard: AB::Var,
channel: impl Into<AB::Expr> + Clone,
channel: &(impl Into<AB::Expr> + Clone),
is_real: AB::Var,
) {
for i in 0..WORD_SIZE {
Expand Down
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