Skip to content

Commit

Permalink
fix: work around #188 by disabling Bn254/Secp256k1 chips
Browse files Browse the repository at this point in the history
  • Loading branch information
wwared committed Oct 21, 2024
1 parent 305b149 commit d6e38e5
Show file tree
Hide file tree
Showing 5 changed files with 33 additions and 23 deletions.
1 change: 1 addition & 0 deletions core/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -79,6 +79,7 @@ neon = ["p3-blake3/neon"]
programs = []
serial = []
avx512 = ["p3-baby-bear/nightly-features"]
enable-all-chips = []

[[bench]]
harness = false
Expand Down
36 changes: 21 additions & 15 deletions core/src/stark/air.rs
Original file line number Diff line number Diff line change
Expand Up @@ -109,11 +109,11 @@ pub enum RiscvAir<F: PrimeField32> {
Bls12381Fp2Op(QuadFieldChip<Bls12381BaseField>),
/// A precompile for decompressing a point on the BLS12-381 curve.
Bls12381G1Decompress(Bls12381G1DecompressChip),
// A precompile for computing round function of Blake2s algorithm
/// A precompile for computing round function of Blake2s algorithm
Blake2sRound(Blake2sRoundChip),
/// A precompile for sha512 extend.
Sha512Extend(Sha512ExtendChip),
/// A precompile for sha256 compress.
/// A precompile for sha512 compress.
Sha512Compress(Sha512CompressChip),
}

Expand All @@ -140,27 +140,29 @@ impl<F: PrimeField32> RiscvAir<F> {
chips.push(RiscvAir::Sha256Extend(sha_extend));
let sha_compress = ShaCompressChip;
chips.push(RiscvAir::Sha256Compress(sha_compress));
let sha512_extend = Sha512ExtendChip;
chips.push(RiscvAir::Sha512Extend(sha512_extend));
let sha512_compress = Sha512CompressChip;
chips.push(RiscvAir::Sha512Compress(sha512_compress));
let ed_add_assign = EdAddAssignChip::<EdwardsCurve<Ed25519Parameters>>::new();
chips.push(RiscvAir::Ed25519Add(ed_add_assign));
let ed_decompress = EdDecompressChip::<Ed25519Parameters>::default();
chips.push(RiscvAir::Ed25519Decompress(ed_decompress));
let k256_decompress = Secp256k1DecompressChip::new();
chips.push(RiscvAir::Secp256k1Decompress(k256_decompress));
let secp256k1_add_assign = WeierstrassAddAssignChip::<SwCurve<Secp256k1Parameters>>::new();
chips.push(RiscvAir::Secp256k1Add(secp256k1_add_assign));
let secp256k1_double_assign =
WeierstrassDoubleAssignChip::<SwCurve<Secp256k1Parameters>>::new();
chips.push(RiscvAir::Secp256k1Double(secp256k1_double_assign));
let keccak_permute = KeccakPermuteChip::new();
chips.push(RiscvAir::KeccakP(keccak_permute));
let bn254_add_assign = WeierstrassAddAssignChip::<SwCurve<Bn254Parameters>>::new();
chips.push(RiscvAir::Bn254Add(bn254_add_assign));
let bn254_double_assign = WeierstrassDoubleAssignChip::<SwCurve<Bn254Parameters>>::new();
chips.push(RiscvAir::Bn254Double(bn254_double_assign));
// NOTE: See issue #188 for more context. Enabling too many chips leads to errors in the recursive verifier.
// These chips below are disabled by default to work around this issue.
cfg_if::cfg_if! {
if #[cfg(feature = "enable-all-chips")] {
let bn254_add_assign = WeierstrassAddAssignChip::<SwCurve<Bn254Parameters>>::new();
chips.push(RiscvAir::Bn254Add(bn254_add_assign));
let bn254_double_assign = WeierstrassDoubleAssignChip::<SwCurve<Bn254Parameters>>::new();
chips.push(RiscvAir::Bn254Double(bn254_double_assign));
let secp256k1_add_assign = WeierstrassAddAssignChip::<SwCurve<Secp256k1Parameters>>::new();
chips.push(RiscvAir::Secp256k1Add(secp256k1_add_assign));
let secp256k1_double_assign =
WeierstrassDoubleAssignChip::<SwCurve<Secp256k1Parameters>>::new();
chips.push(RiscvAir::Secp256k1Double(secp256k1_double_assign));
}
}
let bls12381_g1_add = WeierstrassAddAssignChip::<SwCurve<Bls12381Parameters>>::new();
chips.push(RiscvAir::Bls12381Add(bls12381_g1_add));
let bls12381_g1_double = WeierstrassDoubleAssignChip::<SwCurve<Bls12381Parameters>>::new();
Expand All @@ -173,6 +175,10 @@ impl<F: PrimeField32> RiscvAir<F> {
chips.push(RiscvAir::Bls12381G1Decompress(bls12381_g1_decompress));
let blake_2s_round = Blake2sRoundChip::new();
chips.push(RiscvAir::Blake2sRound(blake_2s_round));
let sha512_extend = Sha512ExtendChip;
chips.push(RiscvAir::Sha512Extend(sha512_extend));
let sha512_compress = Sha512CompressChip;
chips.push(RiscvAir::Sha512Compress(sha512_compress));
let div_rem = DivRemChip;
chips.push(RiscvAir::DivRem(div_rem));

Expand Down
8 changes: 7 additions & 1 deletion core/src/syscall/precompiles/weierstrass/weierstrass_add.rs
Original file line number Diff line number Diff line change
Expand Up @@ -496,7 +496,7 @@ mod tests {
run_test, setup_logger,
tests::{
BLS12381_G1_ADD_ELF, BLS12381_G1_DOUBLE_ELF, BLS12381_G1_SCALARMUL_ELF,
BN254_ADD_ELF, BN254_MUL_ELF, SECP256K1_ADD_ELF, SECP256K1_MUL_ELF,
SECP256K1_ADD_ELF, SECP256K1_MUL_ELF,
},
},
};
Expand All @@ -509,14 +509,20 @@ mod tests {
}

#[test]
#[cfg(feature = "enable-all-chips")]
fn test_bn254_add_simple() {
use crate::utils::tests::BN254_ADD_ELF;

setup_logger();
let program = Program::from(BN254_ADD_ELF);
run_test::<DefaultProver<_, _>>(program).unwrap();
}

#[test]
#[cfg(feature = "enable-all-chips")]
fn test_bn254_mul_simple() {
use crate::utils::tests::BN254_MUL_ELF;

setup_logger();
let program = Program::from(BN254_MUL_ELF);
run_test::<DefaultProver<_, _>>(program).unwrap();
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -531,7 +531,7 @@ pub mod tests {
stark::DefaultProver,
utils::{
run_test, setup_logger,
tests::{BLS12381_G1_DOUBLE_ELF, BN254_DOUBLE_ELF, SECP256K1_DOUBLE_ELF},
tests::{BLS12381_G1_DOUBLE_ELF, SECP256K1_DOUBLE_ELF},
},
};

Expand All @@ -543,7 +543,10 @@ pub mod tests {
}

#[test]
#[cfg(feature = "enable-all-chips")]
fn test_bn254_double_simple() {
use crate::utils::tests::BN254_DOUBLE_ELF;

setup_logger();
let program = Program::from(BN254_DOUBLE_ELF);
run_test::<DefaultProver<_, _>>(program).unwrap();
Expand Down
6 changes: 0 additions & 6 deletions tests/hint-io/Cargo.lock

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

0 comments on commit d6e38e5

Please sign in to comment.