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6.1-rkr1: sync FriendlyElec's DTs from vendor (common, R6S, R6C, T6, CM3588) + add T6-LTS DT #207

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6.1-rkr1: sync FriendlyElec's DTs from vendor (common, R6S, R6C, T6, CM3588) + add T6-LTS DT #207

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2dce094
arm64: dts: sync FriendlyElec's DTs from vendor source (common, R6S, …
rpardini Jul 14, 2024
ae2d00e
arm64: dts: add FriendlyElec's `rk3588-nanopc-t6-lts` DT
rpardini Jul 14, 2024
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1 change: 1 addition & 0 deletions arch/arm64/boot/dts/rockchip/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -291,6 +291,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-w3.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-cm3588-nas.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-android.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-ipc-4x-linux.dtb
Expand Down
7 changes: 6 additions & 1 deletion arch/arm64/boot/dts/rockchip/rk3588-nanopc-cm3588-nas.dts
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Expand Up @@ -79,8 +79,10 @@
status = "disabled";
compatible = "pwm-fan";
#cooling-cells = <2>;
fan-supply = <&vcc5v0_sys>;
pwms = <&pwm1 0 50000 0>;
cooling-levels = <0 50 100 150 200 255>;
cooling-levels = <0 35 64 100 150 255>;
rockchip,hold-time-ms = <2000>;
rockchip,temp-trips = <
50000 1
55000 2
Expand Down Expand Up @@ -293,6 +295,7 @@
status = "okay";

#sound-dai-cells = <1>;
edid-version = <3>;
/* Effective level used to trigger HPD: 0-low, 1-high */
hpd-trigger-level = <1>;
hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
Expand Down Expand Up @@ -419,6 +422,7 @@
};

&i2c8 {
status = "okay";
pinctrl-0 = <&i2c8m2_xfer>;
/* connected with Header_2.54MM */
};
Expand All @@ -429,6 +433,7 @@
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
rockchip,trcm-sync-tx-only;
};

&i2s6_8ch {
Expand Down
29 changes: 29 additions & 0 deletions arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts
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@@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyelec.com)
*/

/dts-v1/;
#include "rk3588-nanopc-t6.dts"

/ {
model = "FriendlyElec NanoPC-T6 LTS";
compatible = "friendlyelec,nanopc-t6", "rockchip,rk3588";

vcc5v0_host_20: vcc5v0-host-20 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host20_en>;
regulator-name = "vcc5v0_host_20";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
};
};

&u2phy3_host {
phy-supply = <&vcc5v0_host_20>;
};
15 changes: 12 additions & 3 deletions arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
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Expand Up @@ -77,8 +77,10 @@
status = "okay";
compatible = "pwm-fan";
#cooling-cells = <2>;
fan-supply = <&vcc5v0_sys>;
pwms = <&pwm1 0 50000 0>;
cooling-levels = <0 50 100 150 200 255>;
cooling-levels = <0 35 64 100 150 255>;
rockchip,hold-time-ms = <2000>;
rockchip,temp-trips = <
50000 1
55000 2
Expand Down Expand Up @@ -208,9 +210,9 @@
};

&hdmi0 {
cec-enable = "true";
enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
status = "okay";
cec-enable = "true";
};

&hdmi0_in_vp0 {
Expand All @@ -230,9 +232,9 @@
};

&hdmi1 {
cec-enable = "true";
enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
status = "okay";
cec-enable = "true";
};

&hdmi1_in_vp0 {
Expand Down Expand Up @@ -260,6 +262,7 @@
status = "okay";

#sound-dai-cells = <1>;
edid-version = <3>;
/* Effective level used to trigger HPD: 0-low, 1-high */
hpd-trigger-level = <1>;
hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
Expand Down Expand Up @@ -406,6 +409,7 @@
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
rockchip,trcm-sync-tx-only;
};

&i2s6_8ch {
Expand Down Expand Up @@ -572,6 +576,11 @@
vcc5v0_host30_en: vcc5v0-host30-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};

/omit-if-no-ref/
vcc5v0_host20_en: vcc5v0-host20-en {
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

Expand Down
42 changes: 41 additions & 1 deletion arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6-common.dtsi
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Expand Up @@ -116,6 +116,10 @@
status = "okay";
};

&avsd {
status = "okay";
};

&combphy0_ps {
status = "okay";
};
Expand Down Expand Up @@ -184,9 +188,9 @@
};

&hdmi0 {
cec-enable;
enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay";
cec-enable = "true";
};

&hdmi0_in_vp0 {
Expand Down Expand Up @@ -526,6 +530,10 @@
status = "okay";
};

&rkvtunnel {
status = "okay";
};

&avcc_1v8_s0 {
regulator-state-mem {
regulator-on-in-suspend;
Expand Down Expand Up @@ -667,6 +675,8 @@
&vop {
assigned-clocks = <&cru ACLK_VOP>;
assigned-clock-rates = <800000000>;
vop-supply = <&vdd_log_s0>;
support-multi-area;
status = "okay";
disable-win-move;
};
Expand Down Expand Up @@ -700,6 +710,29 @@
rockchip,primary-plane = <ROCKCHIP_VOP2_CLUSTER3>;
};

/* TODO: FE has those vps different:
&vp0 {
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>;
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>;
};

&vp1 {
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>;
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
};

&vp2 {
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>;
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>;
};

&vp3 {
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>;
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART3>;
};
*/


&wdt {
status = "okay";
};
Expand All @@ -708,3 +741,10 @@
clocks = <&hdptxphy_hdmi_clk0>;
clock-names = "hdmi0_phy_pll";
};

/* @TODO: FE has display_subsystem different:
&display_subsystem {
clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi0>;
clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
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I think this is only necessary for the boards have 2 HDMI outs

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Makes sense. I guess FriendlyElec devs are economizing: more devices have 2 HDMI inputs so they rather duplicate/override those that don't.

};
*/
14 changes: 13 additions & 1 deletion arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
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Expand Up @@ -24,5 +24,17 @@
};

&pcie2x1l2 {
rockchip,skip-hw-retry;
/delete-node/ pcie@40;
};
};

/* GPIO Connector */
&pwm0 {
pinctrl-0 = <&pwm0m2_pins>;
status = "okay";
};

&pwm1 {
pinctrl-0 = <&pwm1m2_pins>;
status = "okay";
};
10 changes: 10 additions & 0 deletions arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
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Expand Up @@ -176,3 +176,13 @@
status = "okay";
};


&uart4 {
pinctrl-0 = <&uart4m2_xfer>;
status = "disabled";
};

&uart5 {
pinctrl-0 = <&uart5m1_xfer>;
status = "okay";
};
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