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Revert "PCI: rockchip: dw: remove .link_up() hook from struct dw_pcie… #221

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merged 1 commit into from
Aug 16, 2024

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RadxaStephen
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@RadxaStephen RadxaStephen commented Aug 16, 2024

There is one PCIe to SATA controller ASM1164 on ROCK 5 ITX.
This helps resolve the issue where SATA SSDs are sometimes not recognized on ROCK 5 ITX.

AR-2434

…_ops"

Revert this commit as it wasn't reliably work as expected by massive test.
The problem is clear now that cxpl_debug_info from DWC core is missing
rdlh_link_up. So reading PCIE_PORT_DEBUG1 and check smlh_link_up isn't enough.

Quoted from DWC databook, section 8.2.3 AXI Bridge Initialization, Clocking and Reset:

"In RC Mode, your AXI application must not generate any MEM or I/O
requests, until the host software has enabled the Memory Space Enable
(MSE), and IO Space Enable (ISE) bits respectively. Your RC application
should not generate CFG requests until it has confirmed that the link is
up by sampling the smlh_link_up and rdlh_link_up outputs."

The problem was introduced by commit 1 and fixed by commit 2 but not to
the end. And finally commit 3 rename the register but not fix anything.

It was broken from the first time. ANY dwc controller should be use the
buggy default method to check link up state. So revert this commit to use
our own link_up hook, and check PCIE_PORT_DEBUG1_LINK_IN_TRAINING as well
to fix what we were actually trying to fix. This process is confirmed
from ASIC simulation.

[1]. commit dac29e6 ("PCI: designware: Add default link up check if
sub-driver doesn't override")

[2]. commit 01c0767 ("PCI: designware: Check LTSSM training bit
before deciding link is up")

[3]. commit 60ef4b0 ("PCI: dwc: imx6: Share PHY debug register
definitions")

This reverts commit a095b98.

Change-Id: I2104e5fe00ac3be921f6dc1185ad3ce34e01d1bc
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Stephen Chen <stephen@radxa.com>
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nice work!

@igorpecovnik
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I was just getting on this ;) Thanks.

@igorpecovnik igorpecovnik merged commit 16a7adc into armbian:rk-6.1-rkr3 Aug 16, 2024
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@rpardini
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I've been facing some recently-introduced pci/nvme trouble with vendor (6.1-rkr3) kernel; none with 5.10-rkr6.

As far as I can tell, if PCI is enumerated/NVMe scanned during u-boot (and works in u-boot!), then vendor kernel can't see the NVMe.
If I force u-boot to skip the pci/nvme enumeration, then NVMe works when kernel booted (from eMMC).

The vendor u-boot scans NVMe by default if it's enabled in the defconfig and has the correct nodes in DT.

I've the impression this changed between the first drop of 6.1-rkr3 and now, and a quick visual scan reveals this commit shows up as the only PCI-related change in the vendor kernel since the rkr3 drop; I've not investigated u-boot changes yet.

Before I go reverting this locally to test, any opinions? This is on Blade3 btw.

@amazingfate
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If this revert breaks other boards, I think it's better to make it rock5-itx only by introducing a devicetree property.

@Joshua-Riek
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Joshua-Riek commented Sep 19, 2024

I had a few bug reports related to PCIe devices such as the dual NIC not working on the Orange Pi 5 Plus with this commit.

Ref: Joshua-Riek/ubuntu-rockchip#1011

@amazingfate
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The revert commit is from rockchip and from commit msg:

Revert this commit as it wasn't reliably work as expected by massive test.
The problem is clear now that cxpl_debug_info from DWC core is missing
rdlh_link_up. So reading PCIE_PORT_DEBUG1 and check smlh_link_up isn't enough.

When ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000), link_up will return 1.
@rpardini we may add log print to see what's the value of (val & (RDLH_LINKUP | SMLH_LINKUP), and see if we can fix the issue by relaxing the condition.

@amazingfate
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Here is the mainline driver code: https://github.com/torvalds/linux/blob/v6.10/drivers/pci/controller/dwc/pcie-dw-rockchip.c#L158-L160, which is the same as

if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 &&
    (val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY)
        return 1;

While the vendor driver code has

if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000)
    return 1;

Mainline code has extra check (val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY), while both PCIE_LTSSM_STATUS_MASK and PCIE_L0S_ENTRY are not defined in vendor driver.

@amazingfate
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Here is a patch showing result of rk_pcie_readl_apb when rk_pcie_link_up is going to return 1:

diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 94b221b5b614..03c79f0fcd5f 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -281,7 +281,10 @@ static int rk_pcie_link_up(struct dw_pcie *pci)

        val = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS);
        if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000)
+       {
+               dev_info(pci->dev, "%s: val & (RDLH_LINKUP | SMLH_LINKUP) is 0x%lx, val & GENMASK(5, 0) is 0x%lx, going to return 1\n", __func__, (val & (RDLH_LINKUP | SMLH_LINKUP)), (val & GENMASK(5, 0)));
                return 1;
+       }

        return 0;
 }

On rock5b I can see

rk-pcie fe150000.pcie: rk_pcie_link_up: val & (RDLH_LINKUP | SMLH_LINKUP) is 0x30000, val & GENMASK(5, 0) is 0x11, going to return 1

while nvme ssd is still booting.

rpardini added a commit to armsurvivors/armbian-build that referenced this pull request Sep 19, 2024
- somehow when using vendor (not legacy), if nvme scanned during u-boot then won't work in kernel
- See armbian/linux-rockchip#221
rpardini added a commit to armsurvivors/armbian-build that referenced this pull request Sep 19, 2024
- somehow when using vendor (not legacy), if nvme scanned during u-boot then won't work in kernel
- See armbian/linux-rockchip#221
rpardini added a commit to rpardini/armbian-linux-rockchip-rk3588 that referenced this pull request Sep 19, 2024
rpardini added a commit to rpardini/armbian-linux-rockchip-rk3588 that referenced this pull request Sep 19, 2024
rpardini added a commit to armsurvivors/armbian-build that referenced this pull request Sep 19, 2024
- somehow when using vendor (not legacy), if nvme scanned during u-boot then won't work in kernel
- See armbian/linux-rockchip#221
@amazingfate
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@rpardini you can see if this patch can make things better: amazingfate@6b67a8d
This patch will do the same like mainline's driver.

rpardini added a commit to armsurvivors/armbian-build that referenced this pull request Sep 19, 2024
- somehow when using vendor (not legacy), if nvme scanned during u-boot then won't work in kernel
- See armbian/linux-rockchip#221
@rpardini
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Super thanks. I've added the dev_info debug as suggested, but it spews a lot and I'm still parsing to make a comparison between u-boot enumerating and not.

rpardini added a commit to armsurvivors/armbian-build that referenced this pull request Sep 20, 2024
rpardini added a commit to armsurvivors/armbian-build that referenced this pull request Sep 20, 2024
@rpardini
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@rpardini you can see if this patch can make things better: amazingfate@6b67a8d

This makes the NVMe work (5 out of 5 reboots). That is with u-boot enumerating NVMe (as is standard).

Unfortunately, it also makes the RTL8169's not work at all (similar to the report Joshua sent).

For now, the only setup I can arrange that makes both NVMe work in kernel when scanned in u-boot and the ethernets work is fully reverting this PR.

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6 participants