I2S_BITS_PER_SAMPLE_16BIT creates folding around Fs/2 with ICS-43434

[jetpax]

Hi Chris,

Great project !

I noticed that you have folding of the input frequencies around Fs/2.

So for example, your FFT display goes up to 4kHz, but an input signal of 4.1kHz is displayed as 3.9kHz (ie Fs/2-4.1kHz, this alias frequency is apparent even on the time domain plot)

I had similar problems with very different code (MicroPython, though of course still using espidf like Arduino under the hood), with a 1kHz input being aliased to 7kHz (Fs=16000, I2S_BITS_PER_SAMPLE_16BIT )

At first I thought it was ESP-IDF, but it seems it may be related to how the ICS-43434 decimation filter works; the datasheet shows 32 bitclocks per sample, not 16 (w. 24 bits of data).
In any case, I found that using I2S_BITS_PER_SAMPLE_32BIT and dumping the bottom 8 bits fixed the issue for me.

[cgreening]

That is some brilliant detective work! I've pushed up a commit to switch to I2S_BITS_PER_SAMPLE_32BIT.