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WIP: Support atomics #206
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WIP: Support atomics #206
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I also had trouble with gluing all the nodes together. Have asked for help on the llvm-dev list. |
| @@ -157,6 +157,11 @@ AVRTargetLowering::AVRTargetLowering(AVRTargetMachine &tm) | |||
| // improvements in how we treat 16-bit "registers" to be feasible. | |||
| } | |||
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| for (MVT VT : MVT::integer_valuetypes()) { | |||
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I was being lazy originally. I don't think that an i8 needs to have the atomic wrapping as the CPU cannot break it up into pieces.
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LLVMDev suggests that the only real way to do this is in the machine instruction stage. Even if we managed to glue all the nodes together, the pipeline would likely insert spills and stuff inbetween. |
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This adds atomics support to AVR-LLVM. Based of @shepmaster's original work.
Fix for #197