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Compatibility #17

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Compatibility #17

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63f5446
add comments to am5729-beagleboneai.dts
lorforlinux Jun 11, 2020
f019292
easy BBB pinmuxing
lorforlinux Jun 20, 2020
88ace58
easy BBAI pinmuxing
lorforlinux Jun 20, 2020
ef414f3
add bbb-bone-buses.dtsi
lorforlinux Jun 20, 2020
369a235
clean and add bbai-bone-buses.dtsi
lorforlinux Jun 20, 2020
fcdd684
add bone-pinmux-helper nodes
lorforlinux Jun 20, 2020
07dc849
create BBAI /bone/<bus>/<#>
lorforlinux Jun 20, 2020
c42c59a
create BBB /bone/<bus>/<#>
lorforlinux Jun 20, 2020
6280f47
fix tabs
lorforlinux Jun 25, 2020
2a7f9ee
fix spacing
lorforlinux Jun 25, 2020
558c2c3
fix tabs
lorforlinux Jun 25, 2020
86f270c
add comments and fix tabs
lorforlinux Jun 25, 2020
2c22378
add comments and fix tabs
lorforlinux Jun 25, 2020
83a5b91
fix symlink
lorforlinux Jun 27, 2020
ab7d9bf
add BBAI /bone/i2c
lorforlinux Jun 27, 2020
161efee
add BBB /bone/i2c
lorforlinux Jun 27, 2020
d4caaff
add BBAI /bone/spi
lorforlinux Jun 30, 2020
325f881
add BBB /bone/spi
lorforlinux Jun 30, 2020
6eeb085
add P9_13B pin
lorforlinux Jul 6, 2020
857630e
update nodes to use new easy pinmuxing MACROs
lorforlinux Jul 6, 2020
483efd0
fix P9_13 macro reference
lorforlinux Jul 6, 2020
f3d112c
BBAI gpio-leds led_ nodes for compatibility
lorforlinux Jul 7, 2020
795a7b2
BBB gpio-leds led_ nodes for compatibility
lorforlinux Jul 7, 2020
3c67d9e
Initial combined macros for P8 & P9 headers
lorforlinux Jul 10, 2020
878f4c6
Update pin header nodes
lorforlinux Jul 10, 2020
ba85595
fix tabs
lorforlinux Jul 11, 2020
be2da43
add comments
lorforlinux Jul 11, 2020
85c3cb8
cape_pins no longer needed
lorforlinux Jul 12, 2020
bd5af87
Removing macros
lorforlinux Jul 12, 2020
0467b05
Updating pinmuxing nodes
lorforlinux Jul 12, 2020
80879ea
cape_pins node no longer valid
lorforlinux Jul 12, 2020
deba87e
Fix P9_27 bug
lorforlinux Jul 12, 2020
687f01f
BBAI: Remove bone-bus pinmxing in base dtb
lorforlinux Jul 12, 2020
a91ecc9
BBB: remove bone-bus pinmuxing nodes
lorforlinux Jul 12, 2020
c3d3011
BBB: Remove status & pinctrl-names from bone_* nodes
lorforlinux Jul 13, 2020
4552ec0
BBB: add PWM nodes
lorforlinux Jul 13, 2020
a66a07a
BBAI: Remove status & pinctrl-names from bone_* nodes
lorforlinux Jul 13, 2020
5551091
BBAI: add PWM nodes
lorforlinux Jul 13, 2020
bfdaed3
add am5729-bone-pins.h
lorforlinux Jul 15, 2020
e22a7cb
add am335x-bone-pins.h
lorforlinux Jul 15, 2020
9982683
BBB: use pinmux macros
lorforlinux Jul 20, 2020
0566c2c
BBAI: cleanup base dts file
lorforlinux Jul 20, 2020
21068c2
BBAI: updated with dummy nodes
lorforlinux Jul 21, 2020
861db41
BBAI: fix led, spi nodes & add CAN bus
lorforlinux Jul 21, 2020
5a8715f
BBB: fix spi nodes & add CAN bus
lorforlinux Jul 21, 2020
96385ac
add bone bus PWM0
lorforlinux Jul 21, 2020
0091783
BBAI: dummy nodes for bone bus pwm0
lorforlinux Jul 21, 2020
ab632f3
remove symlinks for CAN & PWM
lorforlinux Jul 21, 2020
785fe6f
BBAI: Enabling timer PWM functionality
lorforlinux Jul 29, 2020
56c68f5
BBB: dummy timer nodes
lorforlinux Jul 29, 2020
e40c15c
BBAI: add Timer nodes
lorforlinux Jul 29, 2020
61a7b0e
BBAI: add timer nodes and update spi nodes
lorforlinux Jul 29, 2020
0411005
BBB: add timer nodes and update spi nodes
lorforlinux Jul 29, 2020
97a6f0d
BBAI: add & update PRU nodes
lorforlinux Aug 4, 2020
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86 changes: 86 additions & 0 deletions include/dt-bindings/board/am335x-bone-pins.h
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/*
* Copyright (C) 2020 Deepak Khatri <deepaklorkhatri7@gmail.com>
*
* This program is free software you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/

#ifndef _DT_BINDINGS_BOARD_AM335X_BBB_PINS_H
#define _DT_BINDINGS_BOARD_AM335X_BBB_PINS_H

#define P8_03(mode) AM33XX_IOPAD(0x0818, mode) /* R9: gpmc_ad6 */
#define P8_04(mode) AM33XX_IOPAD(0x081c, mode) /* T9: gpmc_ad7 */
#define P8_05(mode) AM33XX_IOPAD(0x0808, mode) /* R8: gpmc_ad2 */
#define P8_06(mode) AM33XX_IOPAD(0x080c, mode) /* T8: gpmc_ad3 */
#define P8_07(mode) AM33XX_IOPAD(0x0890, mode) /* R7: gpmc_advn_ale */
#define P8_08(mode) AM33XX_IOPAD(0x0894, mode) /* T7: gpmc_oen_ren */
#define P8_09(mode) AM33XX_IOPAD(0x089c, mode) /* T6: gpmc_be0n_cle */
#define P8_10(mode) AM33XX_IOPAD(0x0898, mode) /* U6: gpmc_wen */
#define P8_11(mode) AM33XX_IOPAD(0x0834, mode) /* R12: gpmc_ad13 */
#define P8_12(mode) AM33XX_IOPAD(0x0830, mode) /* T12: gpmc_ad12 */
#define P8_13(mode) AM33XX_IOPAD(0x0824, mode) /* T10: gpmc_ad9 */
#define P8_14(mode) AM33XX_IOPAD(0x0828, mode) /* T11: gpmc_ad10 */
#define P8_15(mode) AM33XX_IOPAD(0x083c, mode) /* U13: gpmc_ad15 */
#define P8_16(mode) AM33XX_IOPAD(0x0838, mode) /* V13: gpmc_ad14 */
#define P8_17(mode) AM33XX_IOPAD(0x082c, mode) /* U12: gpmc_ad11 */
#define P8_18(mode) AM33XX_IOPAD(0x088c, mode) /* V12: gpmc_clk */
#define P8_19(mode) AM33XX_IOPAD(0x0820, mode) /* U10: gpmc_ad8 */
#define P8_20(mode) AM33XX_IOPAD(0x0884, mode) /* V9: gpmc_csn2 */
#define P8_21(mode) AM33XX_IOPAD(0x0880, mode) /* U9: gpmc_csn1 */
#define P8_22(mode) AM33XX_IOPAD(0x0814, mode) /* V8: gpmc_ad5 */
#define P8_23(mode) AM33XX_IOPAD(0x0810, mode) /* U8: gpmc_ad4 */
#define P8_24(mode) AM33XX_IOPAD(0x0804, mode) /* V7: gpmc_ad1 */
#define P8_25(mode) AM33XX_IOPAD(0x0800, mode) /* U7: gpmc_ad0 */
#define P8_26(mode) AM33XX_IOPAD(0x087c, mode) /* V6: gpmc_csn0 */
#define P8_27(mode) AM33XX_IOPAD(0x08e0, mode) /* U5: lcd_vsync */
#define P8_28(mode) AM33XX_IOPAD(0x08e8, mode) /* V5: lcd_pclk */
#define P8_29(mode) AM33XX_IOPAD(0x08e4, mode) /* R5: lcd_hsync */
#define P8_30(mode) AM33XX_IOPAD(0x08ec, mode) /* R6: lcd_ac_bias_en */
#define P8_31(mode) AM33XX_IOPAD(0x08d8, mode) /* V4: lcd_data14 */
#define P8_32(mode) AM33XX_IOPAD(0x08dc, mode) /* T5: lcd_data15 */
#define P8_33(mode) AM33XX_IOPAD(0x08d4, mode) /* V3: lcd_data13 */
#define P8_34(mode) AM33XX_IOPAD(0x08cc, mode) /* U4: lcd_data11 */
#define P8_35(mode) AM33XX_IOPAD(0x08d0, mode) /* V2: lcd_data12 */
#define P8_36(mode) AM33XX_IOPAD(0x08c8, mode) /* U3: lcd_data10 */
#define P8_37(mode) AM33XX_IOPAD(0x08c0, mode) /* U1: lcd_data8 */
#define P8_38(mode) AM33XX_IOPAD(0x08c4, mode) /* U2: lcd_data9 */
#define P8_39(mode) AM33XX_IOPAD(0x08b8, mode) /* T3: lcd_data6 */
#define P8_40(mode) AM33XX_IOPAD(0x08bc, mode) /* T4: lcd_data7 */
#define P8_41(mode) AM33XX_IOPAD(0x08b0, mode) /* T1: lcd_data4 */
#define P8_42(mode) AM33XX_IOPAD(0x08b4, mode) /* T2: lcd_data5 */
#define P8_43(mode) AM33XX_IOPAD(0x08a8, mode) /* R3: lcd_data2 */
#define P8_44(mode) AM33XX_IOPAD(0x08ac, mode) /* R4: lcd_data3 */
#define P8_45(mode) AM33XX_IOPAD(0x08a0, mode) /* R1: lcd_data0 */
#define P8_46(mode) AM33XX_IOPAD(0x08a4, mode) /* R2: lcd_data1 */
#define P9_11(mode) AM33XX_IOPAD(0x0870, mode) /* T17: gpmc_wait0 */
#define P9_12(mode) AM33XX_IOPAD(0x0878, mode) /* U18: gpmc_be1n */
#define P9_13(mode) AM33XX_IOPAD(0x0874, mode) /* U17: gpmc_wpn */
#define P9_14(mode) AM33XX_IOPAD(0x0848, mode) /* U14: gpmc_a2 */
#define P9_15(mode) AM33XX_IOPAD(0x0840, mode) /* R13: gpmc_a0 */
#define P9_16(mode) AM33XX_IOPAD(0x084c, mode) /* T14: gpmc_a3 */
#define P9_17(mode) AM33XX_IOPAD(0x095c, mode) /* A16: spi0_cs0 */
#define P9_18(mode) AM33XX_IOPAD(0x0958, mode) /* B16: spi0_d1 */
#define P9_19(mode) AM33XX_IOPAD(0x097c, mode) /* D17: uart1_rtsn */
#define P9_20(mode) AM33XX_IOPAD(0x0978, mode) /* D18: uart1_ctsn */
#define P9_21(mode) AM33XX_IOPAD(0x0954, mode) /* B17: spi0_d0 */
#define P9_22(mode) AM33XX_IOPAD(0x0950, mode) /* A17: spi0_sclk */
#define P9_23(mode) AM33XX_IOPAD(0x0844, mode) /* V14: gpmc_a1 */
#define P9_24(mode) AM33XX_IOPAD(0x0984, mode) /* D15: uart1_txd */
#define P9_25(mode) AM33XX_IOPAD(0x09ac, mode) /* A14: mcasp0_ahclkx */
#define P9_26(mode) AM33XX_IOPAD(0x0980, mode) /* D16: uart1_rxd */
#define P9_27(mode) AM33XX_IOPAD(0x09a4, mode) /* C13: mcasp0_fsr */
#define P9_28(mode) AM33XX_IOPAD(0x099c, mode) /* C12: mcasp0_ahclkr */
#define P9_29(mode) AM33XX_IOPAD(0x0994, mode) /* B13: mcasp0_fsx */
#define P9_30(mode) AM33XX_IOPAD(0x0998, mode) /* D12: mcasp0_axr0 */
#define P9_31(mode) AM33XX_IOPAD(0x0990, mode) /* A13: mcasp0_aclkx */
#define P9_41(mode) AM33XX_IOPAD(0x09b4, mode) /* D14: xdma_event_intr1 */
#define P9_41A(mode) AM33XX_IOPAD(0x09b4, mode) /* D14: xdma_event_intr1 */
#define P9_41B(mode) AM33XX_IOPAD(0x09a8, mode) /* D13: mcasp0_axr1 */
#define P9_91(mode) AM33XX_IOPAD(0x09a8, mode) /* D13: mcasp0_axr1 */
#define P9_42(mode) AM33XX_IOPAD(0x0964, mode) /* C18: P0_in_PWM0_out */
#define P9_42A(mode) AM33XX_IOPAD(0x0964, mode) /* C18: P0_in_PWM0_out */
#define P9_42B(mode) AM33XX_IOPAD(0x09a0, mode) /* B12: mcasp0_aclkr */
#define P9_92(mode) AM33XX_IOPAD(0x09a0, mode) /* B12: mcasp0_aclkr */

#endif
109 changes: 109 additions & 0 deletions include/dt-bindings/board/am5729-bone-pins.h
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/*
* Copyright (C) 2020 Deepak Khatri <deepaklorkhatri7@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/

#ifndef _DT_BINDINGS_BOARD_AM5729_BBAI_PINS_H
#define _DT_BINDINGS_BOARD_AM5729_BBAI_PINS_H

#define P8_03(mode) DRA7XX_CORE_IOPAD(0x379C, mode) /* AB8: mmc3_dat6 */
#define P8_04(mode) DRA7XX_CORE_IOPAD(0x37A0, mode) /* AB5: mmc3_dat7 */
#define P8_05(mode) DRA7XX_CORE_IOPAD(0x378C, mode) /* AC9: mmc3_dat2 */
#define P8_06(mode) DRA7XX_CORE_IOPAD(0x3790, mode) /* AC3: mmc3_dat3 */
#define P8_07(mode) DRA7XX_CORE_IOPAD(0x36EC, mode) /* G14: mcasp1_axr14 */
#define P8_08(mode) DRA7XX_CORE_IOPAD(0x36F0, mode) /* F14: mcasp1_axr15 */
#define P8_09(mode) DRA7XX_CORE_IOPAD(0x3698, mode) /* E17: xref_clk1 */
#define P8_10(mode) DRA7XX_CORE_IOPAD(0x36E8, mode) /* A13: mcasp1_axr13 */
#define P8_11(mode) DRA7XX_CORE_IOPAD(0x3510, mode) /* AH4: vin1a_d7 */
#define P8_12(mode) DRA7XX_CORE_IOPAD(0x350C, mode) /* AG6: vin1a_d6 */
#define P8_13(mode) DRA7XX_CORE_IOPAD(0x3590, mode) /* D3: vin2a_d10 */
#define P8_14(mode) DRA7XX_CORE_IOPAD(0x3598, mode) /* D5: vin2a_d12 */
#define P8_15A(mode) DRA7XX_CORE_IOPAD(0x3570, mode) /* D1: vin2a_d2 */
#define P8_15B(mode) DRA7XX_CORE_IOPAD(0x35B4, mode) /* A3: vin2a_d19 */
#define P8_16(mode) DRA7XX_CORE_IOPAD(0x35BC, mode) /* B4: vin2a_d21 */
#define P8_17(mode) DRA7XX_CORE_IOPAD(0x3624, mode) /* A7: vout1_d18 */
#define P8_18(mode) DRA7XX_CORE_IOPAD(0x3588, mode) /* F5: vin2a_d8 */
#define P8_19(mode) DRA7XX_CORE_IOPAD(0x358C, mode) /* E6: vin2a_d9 */
#define P8_20(mode) DRA7XX_CORE_IOPAD(0x3780, mode) /* AC4: mmc3_cmd */
#define P8_21(mode) DRA7XX_CORE_IOPAD(0x377C, mode) /* AD4: mmc3_clk */
#define P8_22(mode) DRA7XX_CORE_IOPAD(0x3798, mode) /* AD6: mmc3_dat5 */
#define P8_23(mode) DRA7XX_CORE_IOPAD(0x3794, mode) /* AC8: mmc3_dat4 */
#define P8_24(mode) DRA7XX_CORE_IOPAD(0x3788, mode) /* AC6: mmc3_dat1 */
#define P8_25(mode) DRA7XX_CORE_IOPAD(0x3784, mode) /* AC7: mmc3_dat0 */
#define P8_26(mode) DRA7XX_CORE_IOPAD(0x35B8, mode) /* B3: vin2a_d20 */
#define P8_27A(mode) DRA7XX_CORE_IOPAD(0x35D8, mode) /* E11: vout1_vsync */
#define P8_27B(mode) DRA7XX_CORE_IOPAD(0x3628, mode) /* A8: vout1_d19 */
#define P8_28A(mode) DRA7XX_CORE_IOPAD(0x35C8, mode) /* D11: vout1_clk */
#define P8_28B(mode) DRA7XX_CORE_IOPAD(0x362C, mode) /* C9: vout1_d20 */
#define P8_29A(mode) DRA7XX_CORE_IOPAD(0x35D4, mode) /* C11: vout1_hsync */
#define P8_29B(mode) DRA7XX_CORE_IOPAD(0x3630, mode) /* A9: vout1_d21 */
#define P8_30A(mode) DRA7XX_CORE_IOPAD(0x35CC, mode) /* B10: vout1_de */
#define P8_30B(mode) DRA7XX_CORE_IOPAD(0x3634, mode) /* B9: vout1_d22 */
#define P8_31A(mode) DRA7XX_CORE_IOPAD(0x3614, mode) /* C8: vout1_d14 */
#define P8_31B(mode) DRA7XX_CORE_IOPAD(0x373C, mode) /* G16: mcasp4_axr0 */
#define P8_32A(mode) DRA7XX_CORE_IOPAD(0x3618, mode) /* C7: vout1_d15 */
#define P8_32B(mode) DRA7XX_CORE_IOPAD(0x3740, mode) /* D17: mcasp4_axr1 */
#define P8_33A(mode) DRA7XX_CORE_IOPAD(0x3610, mode) /* C6: vout1_d13 */
#define P8_33B(mode) DRA7XX_CORE_IOPAD(0x34E8, mode) /* AF9: vin1a_fld0 */
#define P8_34A(mode) DRA7XX_CORE_IOPAD(0x3608, mode) /* D8: vout1_d11 */
#define P8_34B(mode) DRA7XX_CORE_IOPAD(0x3564, mode) /* G6: vin2a_vsync0 */
#define P8_35A(mode) DRA7XX_CORE_IOPAD(0x360C, mode) /* A5: vout1_d12 */
#define P8_35B(mode) DRA7XX_CORE_IOPAD(0x34E4, mode) /* AD9: vin1a_de0 */
#define P8_36A(mode) DRA7XX_CORE_IOPAD(0x3604, mode) /* D7: vout1_d10 */
#define P8_36B(mode) DRA7XX_CORE_IOPAD(0x3568, mode) /* F2: vin2a_d0 */
#define P8_37A(mode) DRA7XX_CORE_IOPAD(0x35FC, mode) /* E8: vout1_d8 */
#define P8_37B(mode) DRA7XX_CORE_IOPAD(0x3738, mode) /* A21: mcasp4_fsx */
#define P8_38A(mode) DRA7XX_CORE_IOPAD(0x3600, mode) /* D9: vout1_d9 */
#define P8_38B(mode) DRA7XX_CORE_IOPAD(0x3734, mode) /* C18: mcasp4_aclkx */
#define P8_39(mode) DRA7XX_CORE_IOPAD(0x35F4, mode) /* F8: vout1_d6 */
#define P8_40(mode) DRA7XX_CORE_IOPAD(0x35F8, mode) /* E7: vout1_d7 */
#define P8_41(mode) DRA7XX_CORE_IOPAD(0x35EC, mode) /* E9: vout1_d4 */
#define P8_42(mode) DRA7XX_CORE_IOPAD(0x35F0, mode) /* F9: vout1_d5 */
#define P8_43(mode) DRA7XX_CORE_IOPAD(0x35E4, mode) /* F10: vout1_d2 */
#define P8_44(mode) DRA7XX_CORE_IOPAD(0x35E8, mode) /* G11: vout1_d3 */
#define P8_45A(mode) DRA7XX_CORE_IOPAD(0x35DC, mode) /* F11: vout1_d0 */
#define P8_45B(mode) DRA7XX_CORE_IOPAD(0x361C, mode) /* B7: vout1_d16 */
#define P8_46A(mode) DRA7XX_CORE_IOPAD(0x35E0, mode) /* G10: vout1_d1 */
#define P8_46B(mode) DRA7XX_CORE_IOPAD(0x3638, mode) /* A10: vout1_d23 */
#define P9_11A(mode) DRA7XX_CORE_IOPAD(0x372C, mode) /* B19: mcasp3_axr0 */
#define P9_11B(mode) DRA7XX_CORE_IOPAD(0x3620, mode) /* B8: vout1_d17 */
#define P9_12(mode) DRA7XX_CORE_IOPAD(0x36AC, mode) /* B14: mcasp1_aclkr */
#define P9_13A(mode) DRA7XX_CORE_IOPAD(0x3730, mode) /* C17: mcasp3_axr1 */
#define P9_13B(mode) DRA7XX_CORE_IOPAD(0x3680, mode) /* AB10: usb1_drvvbus */
#define P9_14(mode) DRA7XX_CORE_IOPAD(0x35AC, mode) /* D6: vin2a_d17 */
#define P9_15(mode) DRA7XX_CORE_IOPAD(0x3514, mode) /* AG4: vin1a_d8 */
#define P9_16(mode) DRA7XX_CORE_IOPAD(0x35B0, mode) /* C5: vin2a_d18 */
#define P9_17A(mode) DRA7XX_CORE_IOPAD(0x37CC, mode) /* B24: spi2_cs0 */
#define P9_17B(mode) DRA7XX_CORE_IOPAD(0x36B8, mode) /* F12: mcasp1_axr1 */
#define P9_18A(mode) DRA7XX_CORE_IOPAD(0x37C8, mode) /* G17: spi2_d0 */
#define P9_18B(mode) DRA7XX_CORE_IOPAD(0x36B4, mode) /* G12: mcasp1_axr0 */
#define P9_19A(mode) DRA7XX_CORE_IOPAD(0x3440, mode) /* R6: gpmc_a0.i2c4_scl */
#define P9_19B(mode) DRA7XX_CORE_IOPAD(0x357C, mode) /* F4: vin2a_d5.pr1_pru1_gpi2 */
#define P9_20A(mode) DRA7XX_CORE_IOPAD(0x3444, mode) /* T9: gpmc_a1.i2c4_sda */
#define P9_20B(mode) DRA7XX_CORE_IOPAD(0x3578, mode) /* D2: vin2a_d4.pr1_pru1_gpi1 */
#define P9_21A(mode) DRA7XX_CORE_IOPAD(0x34F0, mode) /* AF8: vin1a_vsync0 */
#define P9_21B(mode) DRA7XX_CORE_IOPAD(0x37C4, mode) /* B22: spi2_d1 */
#define P9_22A(mode) DRA7XX_CORE_IOPAD(0x369C, mode) /* B26: xref_clk2 */
#define P9_22B(mode) DRA7XX_CORE_IOPAD(0x37C0, mode) /* A26: spi2_sclk */
#define P9_23(mode) DRA7XX_CORE_IOPAD(0x37B4, mode) /* A22: spi1_cs1 */
#define P9_24(mode) DRA7XX_CORE_IOPAD(0x368C, mode) /* F20: gpio6_15 */
#define P9_25(mode) DRA7XX_CORE_IOPAD(0x3694, mode) /* D18: xref_clk0 */
#define P9_26A(mode) DRA7XX_CORE_IOPAD(0x3688, mode) /* E21: gpio6_14 */
#define P9_26B(mode) DRA7XX_CORE_IOPAD(0x3544, mode) /* AE2: vin1a_d20 */
#define P9_27A(mode) DRA7XX_CORE_IOPAD(0x35A0, mode) /* C3: vin2a_d14 */
#define P9_27B(mode) DRA7XX_CORE_IOPAD(0x36B0, mode) /* J14: mcasp1_fsr */
#define P9_28(mode) DRA7XX_CORE_IOPAD(0x36E0, mode) /* A12: mcasp1_axr11 */
#define P9_29A(mode) DRA7XX_CORE_IOPAD(0x36D8, mode) /* A11: mcasp1_axr9 */
#define P9_29B(mode) DRA7XX_CORE_IOPAD(0x36A8, mode) /* D14: mcasp1_fsx */
#define P9_30(mode) DRA7XX_CORE_IOPAD(0x36DC, mode) /* B13: mcasp1_axr10 */
#define P9_31A(mode) DRA7XX_CORE_IOPAD(0x36D4, mode) /* B12: mcasp1_axr8 */
#define P9_31B(mode) DRA7XX_CORE_IOPAD(0x36A4, mode) /* C14: mcasp1_aclkx */
#define P9_41A(mode) DRA7XX_CORE_IOPAD(0x36A0, mode) /* C23: xref_clk3 */
#define P9_41B(mode) DRA7XX_CORE_IOPAD(0x3580, mode) /* C1: vin2a_d6 */
#define P9_42A(mode) DRA7XX_CORE_IOPAD(0x36E4, mode) /* E14: mcasp1_axr12 */
#define P9_42B(mode) DRA7XX_CORE_IOPAD(0x359C, mode) /* C2: vin2a_d13 */

#endif
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