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Added Overlay for CTAG Face 2|4 on BBAI and refactored Overlay for BBB
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@RobertCNelson
NiklasWan authored and RobertCNelson committed Jul 1, 2020
1 parent e94880e commit 012b70f
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179 changes: 179 additions & 0 deletions include/dt-bindings/clock/dra7.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2017 Texas Instruments, Inc.
*/
#ifndef __DT_BINDINGS_CLK_DRA7_H
#define __DT_BINDINGS_CLK_DRA7_H

#define DRA7_CLKCTRL_OFFSET 0x20
#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)

/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */

/* mpu clocks */
#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)

/* dsp clocks */
#define DRA7_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)

/* ipu1 clocks */
#define DRA7_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)

/* ipu clocks */
#define DRA7_IPU_CLKCTRL_OFFSET 0x40
#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
#define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
#define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
#define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
#define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
#define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
#define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
#define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)

/* rtc clocks */
#define DRA7_RTC_CLKCTRL_OFFSET 0x40
#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)

/* coreaon clocks */
#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)

/* l3main1 clocks */
#define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
#define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
#define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)

/* ipu2 clocks */
#define DRA7_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)

/* dma clocks */
#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)

/* emif clocks */
#define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)

/* atl clocks */
#define DRA7_ATL_CLKCTRL_OFFSET 0x0
#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
#define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0)

/* l4cfg clocks */
#define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
#define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
#define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
#define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
#define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
#define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
#define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
#define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)

/* l3instr clocks */
#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)

/* dss clocks */
#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)

/* l3init clocks */
#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
#define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0)
#define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8)
#define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0)
#define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
#define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)

/* l4per clocks */
#define DRA7_L4PER_CLKCTRL_OFFSET 0x0
#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc)
#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14)
#define DRA7_PRUSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x18)
#define DRA7_PRUSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x20)
#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
#define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
#define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
#define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
#define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
#define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
#define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
#define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
#define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
#define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
#define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
#define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90)
#define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98)
#define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
#define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
#define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
#define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
#define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
#define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4)
#define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8)
#define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0)
#define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8)
#define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
#define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
#define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
#define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
#define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
#define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
#define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
#define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
#define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130)
#define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138)
#define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
#define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
#define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
#define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
#define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160)
#define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168)
#define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
#define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178)
#define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190)
#define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198)
#define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
#define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
#define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
#define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
#define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
#define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
#define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
#define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
#define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
#define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204)
#define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208)

/* wkupaon clocks */
#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
#define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
#define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)

#endif
156 changes: 101 additions & 55 deletions src/arm/BB-CTAG-SW-8CH-00A0.dts
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Expand Up @@ -10,6 +10,10 @@
/dts-v1/;
/plugin/;

#include <dt-bindings/board/am335x-bbw-bbb-base.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>

/ {
compatible = "ti,beaglebone", "ti,beaglebone-black", "ti,beaglebone-green";

Expand All @@ -35,13 +39,9 @@
/* the hardware ip uses */
"mcasp0", "spi_gpio";

/*
* Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
*/
fragment@0 {
target-path="/";
target-path = "/";
__overlay__ {

chosen {
overlays {
BB-CTAG-SW-8CH-00A0 = __TIMESTAMP__;
Expand Down Expand Up @@ -69,68 +69,99 @@
P8_17_pinmux { status = "disabled"; }; /* spi_cs0 */
};
};

fragment@2 {
target = <&am33xx_pinmux>;
target-path = "/";
__overlay__ {
mcasp0_pins: pinmix_mcasp0_pins {
pinctrl-single,pins = <
0x1ac 0x20 /* mcasp0_ahclkx, MODE0 | INPUT_PULLDOWN | P9_25 */
0x19c 0x02 /* mcasp0_axr2, MODE2 | OUTPUT_PULLDOWN | P9_28 */
0x194 0x20 /* mcasp0_fsx, MODE0 | INPUT_PULLDOWN | P9_29 */
0x190 0x20 /* mcasp0_aclkx, MODE0 | INPUT_PULLDOWN | P9_31 */
0x1a4 0x20 /* mcasp0_fsr, MODE0 | INPUT_PULLDOWN | P9_27 */
0x078 0x26 /* mcasp0_aclkr, MODE6 | INPUT_PULLDOWN | P9_12 */
0x198 0x20 /* mcasp0_axr0, MODE0 | INPUT_PULLDOWN | P9_30 */
>;
};
spi_gpio: spi_gpio {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;

audiocard_spi_pins: pinmux_audiocard_spi_pins {
pinctrl-single,pins = <
0x0DC 0x37 /* spi_sclk, MODE7 | INPUT_PULLUP | SPI_SCLK P8_32 */
0x028 0x37 /* spi_miso, MODE7 | INPUT_PULLUP | SPI_MISO P8_14 */
0x0D4 0x17 /* spi_mosi, MODE7 | OUTPUT_PULLUP | SPI_MOSI P8_33 */
0x02C 0x17 /* spi_cs0, MODE7 | OUTPUT_PULLUP | SPI_CS0 P8_17 */
>;
sck-gpios = <&gpio0 11 0>; //P8.32
mosi-gpios = <&gpio0 9 0>; //P8.33
miso-gpios = <&gpio0 26 0>; //P8.14
cs-gpios = <&gpio0 27 0 &gpio0 10 0>; //P8.17 / P8.31
num-chipselects = <2>;

pinctrl-names = "default";
/* avoid dtc warnings */
pinctrl-0 = <&audiocard_spi_pins>;
status = "okay";

ad193x: ad193x@0{
pinctrl-names = "default";
pinctrl-0 = <&ad1938_codec_reset_muxing>;
#address-cells = <1>;
#size-cells = <0>;

compatible = "analog,ad1938";
status = "okay";
reset-gpio = <&gpio2 17 0>;
reg = <0>; //corresponds to cs
spi-max-frequency = <100000>;
};
};
};
};

fragment@3 {
target = <&spi_gpio>;
target = <&am33xx_pinmux>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&audiocard_spi_pins>;
status = "okay";

/* avoid dtc warnings */
#address-cells = <1>;
#size-cells = <0>;
ad1938_codec_reset_muxing: ad1938_codec_reset_muxing {
pinctrl-single,pins = <
AM33XX_IOPAD (0x8cc, PIN_INPUT_PULLDOWN | MUX_MODE7) /* MODE7 | RESET P8.34 */
>;
};

ad193x: ad193x@0{
#address-cells = <1>;
#size-cells = <0>;
mcasp0_pins_sleep: mcasp0_pins_sleep {
pinctrl-single,pins = <
AM33XX_IOPAD (0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx */
AM33XX_IOPAD (0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_axr2 */
AM33XX_IOPAD (0x994, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_fsx */
AM33XX_IOPAD (0x990, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_aclkx */
AM33XX_IOPAD (0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsr */
AM33XX_IOPAD (0x878, PIN_INPUT_PULLDOWN | MUX_MODE6) /* mcasp0_aclkr */
AM33XX_IOPAD (0x998, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_axr0 */
0x06c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpio1[27] */
>;
};

compatible = "analog,ad1938";
mcasp0_pins: mcasp0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD (0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx */
AM33XX_IOPAD (0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_axr2 */
AM33XX_IOPAD (0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx */
AM33XX_IOPAD (0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx */
AM33XX_IOPAD (0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsr */
AM33XX_IOPAD (0x878, PIN_INPUT_PULLDOWN | MUX_MODE6) /* mcasp0_aclkr */
AM33XX_IOPAD (0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0 */
0x06c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpio1[27] (enable oscillator) */
>;
};

reg = <0>; //corresponds to cs
spi-max-frequency = <100000>;
audiocard_spi_pins: pinmux_audiocard_spi_pins {
pinctrl-single,pins = <
AM33XX_IOPAD (0x8dc, PIN_INPUT_PULLUP | MUX_MODE7) /* spi_sclk, MODE7 | INPUT_PULLUP | SPI_SCLK P8_32 */
AM33XX_IOPAD (0x828, PIN_INPUT_PULLUP | MUX_MODE7) /* spi_miso, MODE7 | INPUT_PULLUP | SPI_MISO P8_14 */
AM33XX_IOPAD (0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE7) /* spi_mosi, MODE7 | OUTPUT_PULLUP | SPI_MOSI P8_33 */
AM33XX_IOPAD (0x82c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* spi_cs0, MODE7 | OUTPUT_PULLUP | SPI_CS0 P8_17 */
>;
};
};
};

fragment@4 {
target = <&mcasp0>;
__overlay__ {
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp0_pins>;

pinctrl-1 = <&mcasp0_pins_sleep>;
status = "okay";

op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <8>;
num-serializer = <16>;
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
2 0 1 0
0 0 0 0
0 0 0 0
Expand All @@ -142,22 +173,37 @@
};

fragment@5 {
target = <&ocp>;
target-path = "/";
__overlay__ {

clk_mcasp0_fixed: clk_mcasp0_fixed {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24576000>;
};

clk_mcasp0: clk_mcasp0 {
#clock-cells = <0>;
compatible = "gpio-gate-clock";
clocks = <&clk_mcasp0_fixed>;
enable-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; /* BeagleBone Black Clk enable on GPIO1_27 */
};

sound {
compatible = "ctag,face-2-4";
model = "CTAG face-2-4 8CH";
audio-codec = <&ad193x>;
mcasp-controller = <&mcasp0>;
audiocard-tdm-slots = <8>;
codec-clock-rate = <24576000>;
cpu-clock-rate = <24576000>;
audio-codec-bit-delay-dac = <1>; //currently only supports 1 or 0 bit delay
audio-codec-bit-delay-adc = <1>;
mcasp-controller-bit-delay-tx = <1>;
mcasp-controller-bit-delay-rx = <1>;
bb-device = <0>; //BBB/BBG
ti,model = "CTAG face-2-4 8CH";
ti,audio-codec = <&ad193x>;
ti,mcasp-controller = <&mcasp0>;
ti,audiocard-tdm-slots = <8>;
ti,codec-clock-rate = <24576000>;
ti,cpu-clock-rate = <24576000>;
status = "okay";

ti,audio-codec-bit-delay-dac = <1>; //currently only supports 1 or 0 bit delay
ti,audio-codec-bit-delay-adc = <1>;
ti,mcasp-controller-bit-delay-tx = <1>;
ti,mcasp-controller-bit-delay-rx = <1>;
bb-device = <0>; //BBB
audio-routing =
"Line Out", "DAC1OUT",
"Line Out", "DAC2OUT",
Expand Down
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