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net: stmmac: xgmac: fix handling of DPP safety error for DMA channels
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Commit 56e58d6 ("net: stmmac: Implement Safety Features in
XGMAC core") checks and reports safety errors, but leaves the
Data Path Parity Errors for each channel in DMA unhandled at all, lead to
a storm of interrupt.
Fix it by checking and clearing the DMA_DPP_Interrupt_Status register.

Fixes: 56e58d6 ("net: stmmac: Implement Safety Features in XGMAC core")
Signed-off-by: Furong Xu <0x1207@gmail.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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@davem330
Furong Xu authored and davem330 committed Feb 2, 2024
1 parent 41b9fb3 commit 46eba19
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Showing 3 changed files with 60 additions and 1 deletion.
1 change: 1 addition & 0 deletions drivers/net/ethernet/stmicro/stmmac/common.h
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Original file line number Diff line number Diff line change
Expand Up @@ -216,6 +216,7 @@ struct stmmac_safety_stats {
unsigned long mac_errors[32];
unsigned long mtl_errors[32];
unsigned long dma_errors[32];
unsigned long dma_dpp_errors[32];
};

/* Number of fields in Safety Stats */
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3 changes: 3 additions & 0 deletions drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
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Original file line number Diff line number Diff line change
Expand Up @@ -303,6 +303,8 @@
#define XGMAC_RXCEIE BIT(4)
#define XGMAC_TXCEIE BIT(0)
#define XGMAC_MTL_ECC_INT_STATUS 0x000010cc
#define XGMAC_MTL_DPP_CONTROL 0x000010e0
#define XGMAC_DDPP_DISABLE BIT(0)
#define XGMAC_MTL_TXQ_OPMODE(x) (0x00001100 + (0x80 * (x)))
#define XGMAC_TQS GENMASK(25, 16)
#define XGMAC_TQS_SHIFT 16
Expand Down Expand Up @@ -385,6 +387,7 @@
#define XGMAC_DCEIE BIT(1)
#define XGMAC_TCEIE BIT(0)
#define XGMAC_DMA_ECC_INT_STATUS 0x0000306c
#define XGMAC_DMA_DPP_INT_STATUS 0x00003074
#define XGMAC_DMA_CH_CONTROL(x) (0x00003100 + (0x80 * (x)))
#define XGMAC_SPH BIT(24)
#define XGMAC_PBLx8 BIT(16)
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57 changes: 56 additions & 1 deletion drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
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Original file line number Diff line number Diff line change
Expand Up @@ -830,6 +830,43 @@ static const struct dwxgmac3_error_desc dwxgmac3_dma_errors[32]= {
{ false, "UNKNOWN", "Unknown Error" }, /* 31 */
};

static const char * const dpp_rx_err = "Read Rx Descriptor Parity checker Error";
static const char * const dpp_tx_err = "Read Tx Descriptor Parity checker Error";
static const struct dwxgmac3_error_desc dwxgmac3_dma_dpp_errors[32] = {
{ true, "TDPES0", dpp_tx_err },
{ true, "TDPES1", dpp_tx_err },
{ true, "TDPES2", dpp_tx_err },
{ true, "TDPES3", dpp_tx_err },
{ true, "TDPES4", dpp_tx_err },
{ true, "TDPES5", dpp_tx_err },
{ true, "TDPES6", dpp_tx_err },
{ true, "TDPES7", dpp_tx_err },
{ true, "TDPES8", dpp_tx_err },
{ true, "TDPES9", dpp_tx_err },
{ true, "TDPES10", dpp_tx_err },
{ true, "TDPES11", dpp_tx_err },
{ true, "TDPES12", dpp_tx_err },
{ true, "TDPES13", dpp_tx_err },
{ true, "TDPES14", dpp_tx_err },
{ true, "TDPES15", dpp_tx_err },
{ true, "RDPES0", dpp_rx_err },
{ true, "RDPES1", dpp_rx_err },
{ true, "RDPES2", dpp_rx_err },
{ true, "RDPES3", dpp_rx_err },
{ true, "RDPES4", dpp_rx_err },
{ true, "RDPES5", dpp_rx_err },
{ true, "RDPES6", dpp_rx_err },
{ true, "RDPES7", dpp_rx_err },
{ true, "RDPES8", dpp_rx_err },
{ true, "RDPES9", dpp_rx_err },
{ true, "RDPES10", dpp_rx_err },
{ true, "RDPES11", dpp_rx_err },
{ true, "RDPES12", dpp_rx_err },
{ true, "RDPES13", dpp_rx_err },
{ true, "RDPES14", dpp_rx_err },
{ true, "RDPES15", dpp_rx_err },
};

static void dwxgmac3_handle_dma_err(struct net_device *ndev,
void __iomem *ioaddr, bool correctable,
struct stmmac_safety_stats *stats)
Expand All @@ -841,6 +878,13 @@ static void dwxgmac3_handle_dma_err(struct net_device *ndev,

dwxgmac3_log_error(ndev, value, correctable, "DMA",
dwxgmac3_dma_errors, STAT_OFF(dma_errors), stats);

value = readl(ioaddr + XGMAC_DMA_DPP_INT_STATUS);
writel(value, ioaddr + XGMAC_DMA_DPP_INT_STATUS);

dwxgmac3_log_error(ndev, value, false, "DMA_DPP",
dwxgmac3_dma_dpp_errors,
STAT_OFF(dma_dpp_errors), stats);
}

static int
Expand Down Expand Up @@ -881,6 +925,12 @@ dwxgmac3_safety_feat_config(void __iomem *ioaddr, unsigned int asp,
value |= XGMAC_TMOUTEN; /* FSM Timeout Feature */
writel(value, ioaddr + XGMAC_MAC_FSM_CONTROL);

/* 5. Enable Data Path Parity Protection */
value = readl(ioaddr + XGMAC_MTL_DPP_CONTROL);
/* already enabled by default, explicit enable it again */
value &= ~XGMAC_DDPP_DISABLE;
writel(value, ioaddr + XGMAC_MTL_DPP_CONTROL);

return 0;
}

Expand Down Expand Up @@ -914,7 +964,11 @@ static int dwxgmac3_safety_feat_irq_status(struct net_device *ndev,
ret |= !corr;
}

err = dma & (XGMAC_DEUIS | XGMAC_DECIS);
/* DMA_DPP_Interrupt_Status is indicated by MCSIS bit in
* DMA_Safety_Interrupt_Status, so we handle DMA Data Path
* Parity Errors here
*/
err = dma & (XGMAC_DEUIS | XGMAC_DECIS | XGMAC_MCSIS);
corr = dma & XGMAC_DECIS;
if (err) {
dwxgmac3_handle_dma_err(ndev, ioaddr, corr, stats);
Expand All @@ -930,6 +984,7 @@ static const struct dwxgmac3_error {
{ dwxgmac3_mac_errors },
{ dwxgmac3_mtl_errors },
{ dwxgmac3_dma_errors },
{ dwxgmac3_dma_dpp_errors },
};

static int dwxgmac3_safety_feat_dump(struct stmmac_safety_stats *stats,
Expand Down

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