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block sketch #271
Merged
Merged
block sketch #271
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Merged
This was referenced Sep 26, 2022
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Implement 'block' sketch, exploiting 64 byte CPU cache lines to increase throughput. Instead of indexing over the full counter table for each lookup, constrain to a 64 byte block, thereby minimizing L1 caches misses. The block is partitioned into 4 segments of 32 counters (still 4 bits) and we guarantee that exactly 1 counter in each segment will be incremented. Since each segment maps to 2 long values in the table this eliminates data dependencies when incrementing.
Final code uses the 'BlockSeg' implementation below. Code for all impls is in commit 8b76d1f.
Frequency
Increment
Eviction throughput