Add Wishbone version of tdpbram

[martijnbastiaan]

We have a true dual port block ram in clash-cores specific for Xilinx:

https://github.com/clash-lang/clash-compiler/blob/c3d197f4d9ecfb34799e22970b1078ffdd773c53/clash-cores/src/Clash/Cores/Xilinx/BlockRam.hs#L22-L63

We'd like to have a Wishbone Classic wrapper around that:

tdpbramWb ::
  forall nAddrs domA domB nBytes a .
  ( HasCallStack
  , KnownNat nAddrs
  , KnownDomain domA
  , KnownDomain domB
  , KnownNat nBytes
  , BitSize a ~ (8 * nBytes)
  , NFDataX a
  , BitPack a
  ) =>

  Clock domA ->
  -- | Port enable
  Enable domA ->

  Signal domA (WishboneM2S .....) ->
  Signal domB (WishboneM2S .....) ->

  ( Signal domA (WishboneS2M .....)
  , Signal domB (WishboneS2M .....)
  )

and (optionally) a circuit wrapper around that:

tdpbramWbC ::
  forall nAddrs domA domB nBytes a .
  ( HasCallStack
  , KnownNat nAddrs
  , KnownDomain domA
  , KnownDomain domB
  , KnownNat nBytes
  , BitSize a ~ (8 * nBytes)
  , NFDataX a
  , BitPack a
  ) =>

  Clock domA ->
  -- | Port enable
  Enable domA ->

  Circuit (Wishbone domA ..., Wishbone domB ...) ()

@Losiek This is a sparsely written issue; make sure to ask questions on #bittide!