Add zacas

bminor · Nov 30, 2023 · ebd1d7f · ebd1d7f
1 parent 0e78c95
commit ebd1d7f
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Showing 8 changed files with 48 additions and 0 deletions.
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
@@ -1118,6 +1118,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"v", "d",		check_implicit_always},
   {"v", "zve64d",	check_implicit_always},
   {"v", "zvl128b",	check_implicit_always},
+  {"zacas", "a",  check_implicit_always},
   {"zvfh", "zvfhmin",	check_implicit_always},
   {"zvfh", "zfhmin",	check_implicit_always},
   {"zvfhmin", "zve32f",	check_implicit_always},
@@ -1268,6 +1269,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zihintpause",	ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
   {"zmmul",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zawrs",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zacas",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfa",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2430,6 +2432,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "a");
     case INSN_CLASS_ZAWRS:
       return riscv_subset_supports (rps, "zawrs");
+    case INSN_CLASS_ZACAS:
+      return riscv_subset_supports (rps, "zacas");
     case INSN_CLASS_F:
       return riscv_subset_supports (rps, "f");
     case INSN_CLASS_D:
@@ -2648,6 +2652,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "a";
     case INSN_CLASS_ZAWRS:
       return "zawrs";
+    case INSN_CLASS_ZACAS:
+      return "zacas";
     case INSN_CLASS_F:
       return "f";
     case INSN_CLASS_D:

diff --git a/gas/testsuite/gas/riscv/zacas-32.d b/gas/testsuite/gas/riscv/zacas-32.d
@@ -0,0 +1,11 @@
+#as: -march=rv32g_zacas
+#source: zacas-32.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+28c5a52f[ 	]+amocas.w[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zacas-32.s b/gas/testsuite/gas/riscv/zacas-32.s
@@ -0,0 +1,2 @@
+target:
+	amocas.w        a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zacas-64.d b/gas/testsuite/gas/riscv/zacas-64.d
@@ -0,0 +1,11 @@
+#as: -march=rv64i_zacas
+#source: zacas-64.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+28c5b52f[ 	]+amocas.d[ 	]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/zacas-64.s b/gas/testsuite/gas/riscv/zacas-64.s
@@ -0,0 +1,2 @@
+target:
+	amocas.d        a0,a1,a2
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
@@ -2320,6 +2320,13 @@
 #define MASK_WRS_NTO 0xffffffff
 #define MATCH_WRS_STO 0x01d00073
 #define MASK_WRS_STO 0xffffffff
+/* Zacas intructions */
+#define MATCH_CAS_W 0x2800202F
+#define MASK_CAS_W 0xFE00707F
+#define MATCH_CAS_D 0x2800302F
+#define MASK_CAS_D 0xFE00707F
+#define MATCH_CAS_Q 0x2800602F
+#define MASK_CAS_Q 0xFE00707F
 /* Vendor-specific (CORE-V) Xcvmac instructions.  */
 #define MATCH_CV_MAC       0x9000302b
 #define MASK_CV_MAC        0xfe00707f

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
@@ -407,6 +407,7 @@ enum riscv_insn_class
   INSN_CLASS_ZIHINTPAUSE,
   INSN_CLASS_ZMMUL,
   INSN_CLASS_ZAWRS,
+  INSN_CLASS_ZACAS,
   INSN_CLASS_F_INX,
   INSN_CLASS_D_INX,
   INSN_CLASS_Q_INX,

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
@@ -988,6 +988,14 @@ const struct riscv_opcode riscv_opcodes[] =
 {"wrs.nto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
 {"wrs.sto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },
 
+/* Zacas instructions */
+{"amocas.w",       0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_W, MASK_CAS_W, match_opcode, 0 },
+{"amocas.d",       0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_D, MASK_CAS_D, match_opcode, 0 },
+{"amocas.q",      64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_Q, MASK_CAS_Q, match_opcode, 0 },
+{"amocas.w.aqrl",  0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQRL, MASK_AMOADD_W|MASK_AQRL, match_opcode, 0 },
+{"amocas.d.aqrl",  0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQRL, MASK_AMOADD_D|MASK_AQRL, match_opcode, 0 },
+{"amocas.q.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOADD_Q|MASK_AQRL, MASK_AMOADD_Q|MASK_AQRL, match_opcode, 0 },
+
 /* Zfa instructions.  */
 {"fli.s",       0, INSN_CLASS_ZFA,         "D,Wfv", MATCH_FLI_S, MASK_FLI_S, match_opcode, 0 },
 {"fli.d",       0, INSN_CLASS_D_AND_ZFA,   "D,Wfv", MATCH_FLI_D, MASK_FLI_D, match_opcode, 0 },