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Add zacas #10

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Add zacas #10

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e63facb
zacas
trdthg Dec 18, 2023
3c2fe47
add aqrl
trdthg Jan 2, 2024
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6 changes: 6 additions & 0 deletions bfd/elfxx-riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1118,6 +1118,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"v", "d", check_implicit_always},
{"v", "zve64d", check_implicit_always},
{"v", "zvl128b", check_implicit_always},
{"zacas", "a", check_implicit_always},
{"zvfh", "zvfhmin", check_implicit_always},
{"zvfh", "zfhmin", check_implicit_always},
{"zvfhmin", "zve32f", check_implicit_always},
Expand Down Expand Up @@ -1275,6 +1276,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
Expand Down Expand Up @@ -2439,6 +2441,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "a");
case INSN_CLASS_ZAWRS:
return riscv_subset_supports (rps, "zawrs");
case INSN_CLASS_ZACAS:
return riscv_subset_supports (rps, "zacas");
case INSN_CLASS_F:
return riscv_subset_supports (rps, "f");
case INSN_CLASS_D:
Expand Down Expand Up @@ -2661,6 +2665,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "a";
case INSN_CLASS_ZAWRS:
return "zawrs";
case INSN_CLASS_ZACAS:
return "zacas";
case INSN_CLASS_F:
return "f";
case INSN_CLASS_D:
Expand Down
17 changes: 17 additions & 0 deletions binutils/.vscode/c_cpp_properties.json
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@@ -0,0 +1,17 @@
{
"configurations": [
{
"name": "Linux",
"includePath": [
"${workspaceFolder}/**",
"/home/trdthg/plct/riscv-gnu-toolchain/build-binutils-newlib/bfd"
],
"defines": [],
"compilerPath": "/etc/profiles/per-user/trdthg/bin/clang",
"cStandard": "c17",
"cppStandard": "c++17",
"intelliSenseMode": "linux-clang-x64"
}
],
"version": 4
}
5 changes: 5 additions & 0 deletions binutils/.vscode/settings.json
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@@ -0,0 +1,5 @@
{
"files.associations": {
"bfd.h": "c"
}
}
17 changes: 17 additions & 0 deletions gas/testsuite/gas/riscv/zacas-128.d
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@@ -0,0 +1,17 @@
#as: -march=rv64i_zacas
#source: zacas-128.s
#objdump: -d

.*:[ ]+file format .*

Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+28b6652f[ ]+amocas.q[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+28b6652f[ ]+amocas.q[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2cb6652f[ ]+amocas.q.aq[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2cb6652f[ ]+amocas.q.aq[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2ab6652f[ ]+amocas.q.rl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2ab6652f[ ]+amocas.q.rl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2eb6652f[ ]+amocas.q.aqrl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2eb6652f[ ]+amocas.q.aqrl[ ]+a0,a1,\(a2\)
9 changes: 9 additions & 0 deletions gas/testsuite/gas/riscv/zacas-128.s
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@@ -0,0 +1,9 @@
target:
amocas.q a0,a1,0(a2)
amocas.q a0,a1,(a2)
amocas.q.aq a0,a1,0(a2)
amocas.q.aq a0,a1,(a2)
amocas.q.rl a0,a1,0(a2)
amocas.q.rl a0,a1,(a2)
amocas.q.aqrl a0,a1,0(a2)
amocas.q.aqrl a0,a1,(a2)
26 changes: 26 additions & 0 deletions gas/testsuite/gas/riscv/zacas-32.d
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#as: -march=rv32i_zacas
#source: zacas-32.s
#objdump: -d

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+28b6252f[ ]+amocas.w[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+28b6252f[ ]+amocas.w[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2cb6252f[ ]+amocas.w.aq[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2cb6252f[ ]+amocas.w.aq[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2ab6252f[ ]+amocas.w.rl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2ab6252f[ ]+amocas.w.rl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2eb6252f[ ]+amocas.w.aqrl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2eb6252f[ ]+amocas.w.aqrl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+28b6352f[ ]+amocas.d[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+28b6352f[ ]+amocas.d[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2cb6352f[ ]+amocas.d.aq[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2cb6352f[ ]+amocas.d.aq[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2ab6352f[ ]+amocas.d.rl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2ab6352f[ ]+amocas.d.rl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2eb6352f[ ]+amocas.d.aqrl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2eb6352f[ ]+amocas.d.aqrl[ ]+a0,a1,\(a2\)
17 changes: 17 additions & 0 deletions gas/testsuite/gas/riscv/zacas-32.s
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target:
amocas.w a0,a1,0(a2)
amocas.w a0,a1,(a2)
amocas.w.aq a0,a1,0(a2)
amocas.w.aq a0,a1,(a2)
amocas.w.rl a0,a1,0(a2)
amocas.w.rl a0,a1,(a2)
amocas.w.aqrl a0,a1,0(a2)
amocas.w.aqrl a0,a1,(a2)
amocas.d a0,a1,0(a2)
amocas.d a0,a1,(a2)
amocas.d.aq a0,a1,0(a2)
amocas.d.aq a0,a1,(a2)
amocas.d.rl a0,a1,0(a2)
amocas.d.rl a0,a1,(a2)
amocas.d.aqrl a0,a1,0(a2)
amocas.d.aqrl a0,a1,(a2)
26 changes: 26 additions & 0 deletions gas/testsuite/gas/riscv/zacas-64.d
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@@ -0,0 +1,26 @@
#as: -march=rv64i_zacas
#source: zacas-64.s
#objdump: -d

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <target>:
[ ]+[0-9a-f]+:[ ]+28b6252f[ ]+amocas.w[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+28b6252f[ ]+amocas.w[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2cb6252f[ ]+amocas.w.aq[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2cb6252f[ ]+amocas.w.aq[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2ab6252f[ ]+amocas.w.rl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2ab6252f[ ]+amocas.w.rl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2eb6252f[ ]+amocas.w.aqrl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2eb6252f[ ]+amocas.w.aqrl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+28b6352f[ ]+amocas.d[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+28b6352f[ ]+amocas.d[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2cb6352f[ ]+amocas.d.aq[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2cb6352f[ ]+amocas.d.aq[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2ab6352f[ ]+amocas.d.rl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2ab6352f[ ]+amocas.d.rl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2eb6352f[ ]+amocas.d.aqrl[ ]+a0,a1,\(a2\)
[ ]+[0-9a-f]+:[ ]+2eb6352f[ ]+amocas.d.aqrl[ ]+a0,a1,\(a2\)
17 changes: 17 additions & 0 deletions gas/testsuite/gas/riscv/zacas-64.s
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target:
amocas.w a0,a1,0(a2)
amocas.w a0,a1,(a2)
amocas.w.aq a0,a1,0(a2)
amocas.w.aq a0,a1,(a2)
amocas.w.rl a0,a1,0(a2)
amocas.w.rl a0,a1,(a2)
amocas.w.aqrl a0,a1,0(a2)
amocas.w.aqrl a0,a1,(a2)
amocas.d a0,a1,0(a2)
amocas.d a0,a1,(a2)
amocas.d.aq a0,a1,0(a2)
amocas.d.aq a0,a1,(a2)
amocas.d.rl a0,a1,0(a2)
amocas.d.rl a0,a1,(a2)
amocas.d.aqrl a0,a1,0(a2)
amocas.d.aqrl a0,a1,(a2)
7 changes: 7 additions & 0 deletions include/opcode/riscv-opc.h
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Expand Up @@ -2320,6 +2320,13 @@
#define MASK_WRS_NTO 0xffffffff
#define MATCH_WRS_STO 0x01d00073
#define MASK_WRS_STO 0xffffffff
/* Zacas intructions */
#define MATCH_CAS_W 0x2800202F
#define MASK_CAS_W 0xFE00707F
#define MATCH_CAS_D 0x2800302F
#define MASK_CAS_D 0xFE00707F
#define MATCH_CAS_Q 0x2800602F
#define MASK_CAS_Q 0xFE00707F
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
Expand Down
1 change: 1 addition & 0 deletions include/opcode/riscv.h
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Expand Up @@ -413,6 +413,7 @@ enum riscv_insn_class
INSN_CLASS_ZIHINTPAUSE,
INSN_CLASS_ZMMUL,
INSN_CLASS_ZAWRS,
INSN_CLASS_ZACAS,
INSN_CLASS_F_INX,
INSN_CLASS_D_INX,
INSN_CLASS_Q_INX,
Expand Down
14 changes: 14 additions & 0 deletions opcodes/riscv-opc.c
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Expand Up @@ -988,6 +988,20 @@ const struct riscv_opcode riscv_opcodes[] =
{"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
{"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },

/* Zacas instructions */
{"amocas.w", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_W, MASK_CAS_W, match_opcode, 0 },
{"amocas.d", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_D, MASK_CAS_D, match_opcode, 0 },
{"amocas.q", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_Q, MASK_CAS_Q, match_opcode, 0 },
{"amocas.w.aq", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_W|MASK_AQ, MASK_CAS_W|MASK_AQ, match_opcode, 0 },
{"amocas.d.aq", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_D|MASK_AQ, MASK_CAS_D|MASK_AQ, match_opcode, 0 },
{"amocas.q.aq", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_Q|MASK_AQ, MASK_CAS_Q|MASK_AQ, match_opcode, 0 },
{"amocas.w.rl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_W|MASK_RL, MASK_CAS_W|MASK_RL, match_opcode, 0 },
{"amocas.d.rl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_D|MASK_RL, MASK_CAS_D|MASK_RL, match_opcode, 0 },
{"amocas.q.rl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_Q|MASK_RL, MASK_CAS_Q|MASK_RL, match_opcode, 0 },
{"amocas.w.aqrl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_W|MASK_AQRL, MASK_CAS_W|MASK_AQRL, match_opcode, 0 },
{"amocas.d.aqrl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_D|MASK_AQRL, MASK_CAS_D|MASK_AQRL, match_opcode, 0 },
{"amocas.q.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_Q|MASK_AQRL, MASK_CAS_Q|MASK_AQRL, match_opcode, 0 },

/* Zfa instructions. */
{"fli.s", 0, INSN_CLASS_ZFA, "D,Wfv", MATCH_FLI_S, MASK_FLI_S, match_opcode, 0 },
{"fli.d", 0, INSN_CLASS_D_AND_ZFA, "D,Wfv", MATCH_FLI_D, MASK_FLI_D, match_opcode, 0 },
Expand Down