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briansmith opened this issue Aug 30, 2015 · 2 comments
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Remove casts to size_t in Rust code #4

briansmith opened this issue Aug 30, 2015 · 2 comments
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static-analysis-and-type-safety

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@briansmith
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See rust-lang/rust/#28096.

There are some casts like digest.len() as libc::size_t that are potentially truncating and thus unsafe. At the same time, the comments in the code questioning the safety of such casts need to be removed.

This will have to wait for a higher-versioned released of the libc crate with rust-lang/rust#28096 merged into it.
@briansmith
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This depends on rust-lang/rust#28779. That was merged to the Rust beta branch in rust-lang/rust#29112 so we can probably do this soon.

@briansmith briansmith mentioned this issue Oct 18, 2015
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@briansmith
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Fixed in 377f611 by dropping the dependency on the libc crate and defining our own size_t type: ring::c::size_t.

@briansmith briansmith mentioned this issue Jun 4, 2016
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@briansmith briansmith mentioned this issue Oct 25, 2016
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@jamesmunns jamesmunns mentioned this issue Jul 14, 2017
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tomaka pushed a commit to tomaka/ring that referenced this issue Jul 4, 2018
@debris
Merge pull request briansmith#4 from tomaka/fix-build2
957f8fc 
Fix the build
backwardn pushed a commit to backwardn/ring that referenced this issue Nov 20, 2019
Merge pull request briansmith#4 from xnum/master
7b27005 
Fix generateMultiHash write data to source data slice
briansmith added a commit that referenced this issue Apr 8, 2025
@briansmith
cpu: Use relaxed ordering on AArch64.
f40ee29 
This changes the codegen for places where we call `cpu::features()` as expected.

Examples:

```
 	adrp	x8, :got:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E
 	mov	x19, x0
	ldr	x8, [x8, :got_lo12:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E]
-	ldar	x8, [x8]
+	ldr	x8, [x8]
 	cbz	x8, .LBB86_2
```

```
 	adrp	x8, :got:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E
 	mov	x19, x4
 	mov	x20, x3
 	ldr	x8, [x8, :got_lo12:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E]
 	mov	x21, x2
 	mov	x22, x0
 	sub	x23, x3, #4
-	ldar	x8, [x8]
+	ldr	x8, [x8]
 	cbz	x8, .LBB84_8
```
briansmith added a commit that referenced this issue Apr 10, 2025
@briansmith
cpu: Use relaxed ordering on AArch64.
6b358c2 
This changes the codegen for places where we call `cpu::features()` as expected.

Examples:

```
 	adrp	x8, :got:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E
 	mov	x19, x0
	ldr	x8, [x8, :got_lo12:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E]
-	ldar	x8, [x8]
+	ldr	x8, [x8]
 	cbz	x8, .LBB86_2
```

```
 	adrp	x8, :got:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E
 	mov	x19, x4
 	mov	x20, x3
 	ldr	x8, [x8, :got_lo12:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E]
 	mov	x21, x2
 	mov	x22, x0
 	sub	x23, x3, #4
-	ldar	x8, [x8]
+	ldr	x8, [x8]
 	cbz	x8, .LBB84_8
```
briansmith added a commit that referenced this issue Apr 10, 2025
@briansmith
cpu: Use relaxed ordering on AArch64.
2a76fe4 
This changes the codegen for places where we call `cpu::features()` as expected.

Examples:

```
 	adrp	x8, :got:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E
 	mov	x19, x0
	ldr	x8, [x8, :got_lo12:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E]
-	ldar	x8, [x8]
+	ldr	x8, [x8]
 	cbz	x8, .LBB86_2
```

```
 	adrp	x8, :got:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E
 	mov	x19, x4
 	mov	x20, x3
 	ldr	x8, [x8, :got_lo12:_ZN4ring3cpu3arm12featureflags8FEATURES17habb4a2487137fb15E]
 	mov	x21, x2
 	mov	x22, x0
 	sub	x23, x3, #4
-	ldar	x8, [x8]
+	ldr	x8, [x8]
 	cbz	x8, .LBB84_8
```
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