Merge pull request #7 from pan-/ble_integration

Ble integration
bridadan · Jun 21, 2016 · 089143e · 089143e
2 parents 6afe131 + 05fea6e
commit 089143e
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Showing 132 changed files with 749 additions and 37,999 deletions.
diff --git a/hal/targets.json b/hal/targets.json
@@ -1100,7 +1100,13 @@
         "inherits": ["Target"],
         "core": "Cortex-M0",
         "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
-        "macros": ["NRF51", "TARGET_NRF51822"],
+        "macros": [
+            "NRF51",
+            "TARGET_NRF51822",
+            "BLE_STACK_SUPPORT_REQD",
+            "SOFTDEVICE_PRESENT",
+            "S130"
+        ],
         "MERGE_BOOTLOADER": false,
         "extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822", "NRF5"],
         "OUTPUT_EXT": "hex",
@@ -1110,37 +1116,18 @@
         "MERGE_SOFT_DEVICE": true,
         "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
             {
-                "boot": "s130_nrf51_1.0.0_bootloader.hex",
-                "name": "s130_nrf51_1.0.0_softdevice.hex",
-                "offset": 114688
-            },
-            {
-                "boot": "s110_nrf51822_8.0.0_bootloader.hex",
-                "name": "s110_nrf51822_8.0.0_softdevice.hex",
-                "offset": 98304
-            },
-            {
-                "boot": "s110_nrf51822_7.1.0_bootloader.hex",
-                "name": "s110_nrf51822_7.1.0_softdevice.hex",
-                "offset": 90112
-            },
-            {
-                "boot": "s110_nrf51822_7.0.0_bootloader.hex",
-                "name": "s110_nrf51822_7.0.0_softdevice.hex",
-                "offset": 90112
-            },
-            {
-                "boot": "s110_nrf51822_6.0.0_bootloader.hex",
-                "name": "s110_nrf51822_6.0.0_softdevice.hex",
-                "offset": 81920
+                "boot": "",
+                "name": "s130_nrf51_2.0.0_softdevice.hex",
+                "offset": 110592
             }
         ],
         "detect_code": ["1070"],
         "post_binary_hook": {
             "function": "MCU_NRF51Code.binary_hook",
             "toolchains": ["ARM_STD", "GCC_ARM"]
         },
-        "program_cycle_s": 6
+        "program_cycle_s": 6,
+        "features": ["BLE"]
     },
     "MCU_NRF51_16K_BASE": {
         "inherits": ["MCU_NRF51"],
@@ -1738,7 +1725,7 @@
     "MCU_NRF52": {
         "inherits": ["Target"],
         "core": "Cortex-M4F",
-        "macros": ["NRF52", "TARGET_NRF52832"],
+        "macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132"],
         "extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5"],
         "OUTPUT_EXT": "hex",
         "is_disk_virtual": true,
@@ -1758,12 +1745,34 @@
             "function": "MCU_NRF51Code.binary_hook",
             "toolchains": ["ARM_STD", "GCC_ARM"]
         },
-        "MERGE_BOOTLOADER": false
+        "MERGE_BOOTLOADER": false,
+        "features": ["BLE"]
     },
     "NRF52_DK": {
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF52"],
         "progen": {"target": "nrf52-dk"},
+        "macros_add": [
+            "BOARD_PCA10040",
+            "NRF52_PAN_12",
+            "NRF52_PAN_15",
+            "NRF52_PAN_58",
+            "NRF52_PAN_55",
+            "NRF52_PAN_54",
+            "NRF52_PAN_31",
+            "NRF52_PAN_30",
+            "NRF52_PAN_51",
+            "NRF52_PAN_36",
+            "NRF52_PAN_53",
+            "S132",
+            "CONFIG_GPIO_AS_PINRESET",
+            "BLE_STACK_SUPPORT_REQD",
+            "SWI_DISABLE0",
+            "NRF52_PAN_20",
+            "NRF52_PAN_64",
+            "NRF52_PAN_62",
+            "NRF52_PAN_63"
+        ],
         "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
     }
 }
diff --git a/...ORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld b/...ORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld
@@ -2,8 +2,8 @@
 
 MEMORY
 {
-  FLASH (rx) : ORIGIN = 0x0001C000, LENGTH = 0x24000
-  RAM (rwx) :  ORIGIN = 0x20002800, LENGTH = 0x5800
+  FLASH (rx) : ORIGIN = 0x0001B000, LENGTH = 0x25000
+  RAM (rwx) :  ORIGIN = 0x20002ef8, LENGTH = 0x5108
 }
 
 OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
@@ -114,6 +114,15 @@ SECTIONS
 
 	} > RAM
 
+    __edata = .;
+
+    .fs_data :
+    {
+      PROVIDE(__start_fs_data = .);
+      KEEP(*(.fs_data))
+      PROVIDE(__stop_fs_data = .);
+    } > RAM
+
 	.bss :
 	{
 		. = ALIGN(4);

diff --git a/.../cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/startup_NRF51822.S b/.../cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/startup_NRF51822.S
@@ -117,8 +117,9 @@ __Vectors:
 
 /* Reset Handler */
 
-    .equ    NRF_POWER_RAMON_ADDRESS,            0x40000524
-    .equ    NRF_POWER_RAMON_RAMxON_ONMODE_Msk,  0x3
+    .equ    NRF_POWER_RAMON_ADDRESS,             0x40000524
+    .equ    NRF_POWER_RAMONB_ADDRESS,            0x40000554
+    .equ    NRF_POWER_RAMONx_RAMxON_ONMODE_Msk,  0x3  
 
     .text
     .thumb
@@ -129,10 +130,14 @@ __Vectors:
 Reset_Handler:
     .fnstart
 
-/* Make sure ALL RAM banks are powered on */
+    MOVS    R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
     LDR     R0, =NRF_POWER_RAMON_ADDRESS
     LDR     R2, [R0]
-    MOVS    R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
+    ORRS    R2, R1
+    STR     R2, [R0]
+
+    LDR     R0, =NRF_POWER_RAMONB_ADDRESS
+    LDR     R2, [R0]
     ORRS    R2, R1
     STR     R2, [R0]
 

diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/system_nrf51.c b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/system_nrf51.c
@@ -94,6 +94,14 @@ void SystemInit(void)
         }
         *(uint32_t volatile *)0x4006EC14 = 0xC0;
     }
+
+    NRF_CLOCK->LFCLKSRC            = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
+    NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
+    NRF_CLOCK->TASKS_LFCLKSTART    = 1;
+
+    while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
+        // wait for the low frequency clock start
+    }
 }
 
 

diff --git a/...targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_GCC_ARM/NRF52832.ld b/...targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_GCC_ARM/NRF52832.ld
@@ -83,7 +83,6 @@ SECTIONS
         KEEP(*(.eh_frame*))
     } > FLASH
 
-
     .ARM.extab :
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)

diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/system_nrf52.c b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/system_nrf52.c
@@ -187,6 +187,15 @@ void SystemInit(void)
     #endif
 
     SystemCoreClockUpdate();
+
+    NRF_CLOCK->LFCLKSRC            = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
+    NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
+    NRF_CLOCK->TASKS_LFCLKSTART    = 1;
+
+    while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
+        // wait for the low frequency clock start
+    }
+
 }
 
 

diff --git a/...RF5/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_licence_agreement.txt b/...RF5/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_licence_agreement.txt