Add pmu-events json for Rainier

Generated from https://github.com/ARM-software/data/blob/master/pmu/rainier.json using https://gitlab.arm.com/telemetry-solution/telemetry-solution/-/tree/main/tools/perf_json_generator: `/generate.py <cheribsd>/lib/libpmc --arm-data-path <arm-data> --arm-data-cpus rainier`
bsdjhb · Aug 30, 2023 · c3dbecd · c3dbecd
1 parent 1f81d5c
commit c3dbecd
Show file tree

Hide file tree

Showing 9 changed files with 741 additions and 0 deletions.
diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/rainier/branch.json b/lib/libpmc/pmu-events/arch/arm64/arm/rainier/branch.json
@@ -0,0 +1,22 @@
+[
+    {
+        "ArchStdEvent": "BR_MIS_PRED",
+        "PublicDescription": "Mispredicted or not predicted branch speculatively executed. This event counts any predictable branch instruction which is mispredicted either due to dynamic misprediction or because the MMU is off and the branches are statically predicted not taken"
+    },
+    {
+        "ArchStdEvent": "BR_PRED",
+        "PublicDescription": "Predictable branch speculatively executed. This event counts all predictable branches"
+    },
+    {
+        "ArchStdEvent": "BR_IMMED_SPEC",
+        "PublicDescription": "Branch speculatively executed, immediate branch"
+    },
+    {
+        "ArchStdEvent": "BR_RETURN_SPEC",
+        "PublicDescription": "Branch speculatively executed, procedure return"
+    },
+    {
+        "ArchStdEvent": "BR_INDIRECT_SPEC",
+        "PublicDescription": "Branch speculatively executed, indirect branch"
+    }
+]
diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/rainier/bus.json b/lib/libpmc/pmu-events/arch/arm64/arm/rainier/bus.json
@@ -0,0 +1,34 @@
+[
+    {
+        "ArchStdEvent": "CPU_CYCLES",
+        "PublicDescription": "Cycle"
+    },
+    {
+        "ArchStdEvent": "BUS_ACCESS",
+        "PublicDescription": "Bus access. This event counts for every beat of data transferred over the data channels between the core and the SCU. If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD and BUS_ACCESS_WR"
+    },
+    {
+        "ArchStdEvent": "BUS_CYCLES",
+        "PublicDescription": "Bus cycles. This event duplicates CPU_CYCLES"
+    },
+    {
+        "ArchStdEvent": "BUS_ACCESS_RD",
+        "PublicDescription": "Bus access read. This event counts for every beat of data transferred over the read data channel between the core and the SCU"
+    },
+    {
+        "ArchStdEvent": "BUS_ACCESS_WR",
+        "PublicDescription": "Bus access write. This event counts for every beat of data transferred over the write data channel between the core and the SCU"
+    },
+    {
+        "PublicDescription": "Bus access, read, valid capability. The counter counts each access counted by BUS_ACCESS_RD where a Capability Tag was set in at least one beat of the access",
+        "EventCode": "0x22D",
+        "EventName": "BUS_ACCESS_RD_CTAG",
+        "BriefDescription": "Bus access, read, valid capability. The counter counts each access counted by BUS_ACCESS_RD where a Capability Tag was set in at least one beat of the access"
+    },
+    {
+        "PublicDescription": "Bus access, write, valid capability. The counter counts each access counted by BUS_ACCESS_WR where a Capability Tag was set in at least one beat of the access",
+        "EventCode": "0x22E",
+        "EventName": "BUS_ACCESS_WR_CTAG",
+        "BriefDescription": "Bus access, write, valid capability. The counter counts each access counted by BUS_ACCESS_WR where a Capability Tag was set in at least one beat of the access"
+    }
+]
diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/rainier/cache.json b/lib/libpmc/pmu-events/arch/arm64/arm/rainier/cache.json
diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/rainier/exception.json b/lib/libpmc/pmu-events/arch/arm64/arm/rainier/exception.json
@@ -0,0 +1,62 @@
+[
+    {
+        "ArchStdEvent": "EXC_TAKEN",
+        "PublicDescription": "Exception taken"
+    },
+    {
+        "ArchStdEvent": "MEMORY_ERROR",
+        "PublicDescription": "Local memory error. This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs"
+    },
+    {
+        "ArchStdEvent": "EXC_UNDEF",
+        "PublicDescription": "Counts the number of undefined exceptions taken locally"
+    },
+    {
+        "ArchStdEvent": "EXC_SVC",
+        "PublicDescription": "Exception taken locally, Supervisor Call"
+    },
+    {
+        "ArchStdEvent": "EXC_PABORT",
+        "PublicDescription": "Exception taken locally, Instruction Abort"
+    },
+    {
+        "ArchStdEvent": "EXC_DABORT",
+        "PublicDescription": "Exception taken locally, Data Abort and SError"
+    },
+    {
+        "ArchStdEvent": "EXC_IRQ",
+        "PublicDescription": "Exception taken locally, IRQ"
+    },
+    {
+        "ArchStdEvent": "EXC_FIQ",
+        "PublicDescription": "Exception taken locally, FIQ"
+    },
+    {
+        "ArchStdEvent": "EXC_SMC",
+        "PublicDescription": "Exception taken locally, Secure Monitor Call"
+    },
+    {
+        "ArchStdEvent": "EXC_HVC",
+        "PublicDescription": "Exception taken locally, Hypervisor Call"
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_PABORT",
+        "PublicDescription": "Exception taken, Instruction Abort not taken locally"
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_DABORT",
+        "PublicDescription": "Exception taken, Data Abort or SError not taken locally"
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_OTHER",
+        "PublicDescription": "Exception taken, Other traps not taken locally"
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_IRQ",
+        "PublicDescription": "Exception taken, IRQ not taken locally"
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_FIQ",
+        "PublicDescription": "Exception taken, FIQ not taken locally"
+    }
+]
diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/rainier/instruction.json b/lib/libpmc/pmu-events/arch/arm64/arm/rainier/instruction.json
@@ -0,0 +1,168 @@
+[
+    {
+        "ArchStdEvent": "SW_INCR",
+        "PublicDescription": "Software increment. Instruction architecturally executed (condition code check pass)"
+    },
+    {
+        "ArchStdEvent": "INST_RETIRED",
+        "PublicDescription": "Instruction architecturally executed. This event counts all retired instructions, including those that fail their condition check"
+    },
+    {
+        "ArchStdEvent": "EXC_RETURN",
+        "PublicDescription": "Instruction architecturally executed, condition code check pass, exception return"
+    },
+    {
+        "ArchStdEvent": "CID_WRITE_RETIRED",
+        "PublicDescription": "Instruction architecturally executed, condition code check pass, write to CONTEXTIDR. This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state. The following instructions are not counted:\nWrites to CONTEXTIDR_EL12 and CONTEXTIDR_EL2"
+    },
+    {
+        "ArchStdEvent": "INST_SPEC",
+        "PublicDescription": "Operation speculatively executed"
+    },
+    {
+        "ArchStdEvent": "TTBR_WRITE_RETIRED",
+        "PublicDescription": "Instruction architecturally executed, condition code check pass, write to TTBR.This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state. The following instructions are not counted:\nAccesses to TTBR0_EL12/TTBR1_EL12 or TTBR0_EL2/ TTBR1_EL2"
+    },
+    {
+        "ArchStdEvent": "BR_RETIRED",
+        "PublicDescription": "Instruction architecturally executed, branch. This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches"
+    },
+    {
+        "ArchStdEvent": "BR_MIS_PRED_RETIRED",
+        "PublicDescription": "Instruction architecturally executed, mispredicted branch. This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush"
+    },
+    {
+        "ArchStdEvent": "LDREX_SPEC",
+        "PublicDescription": "Exclusive operation speculatively executed, LDREX or LDX"
+    },
+    {
+        "ArchStdEvent": "STREX_PASS_SPEC",
+        "PublicDescription": "Exclusive operation speculatively executed, STREX or STX pass"
+    },
+    {
+        "ArchStdEvent": "STREX_FAIL_SPEC",
+        "PublicDescription": "Exclusive operation speculatively executed, STREX or STX fail"
+    },
+    {
+        "ArchStdEvent": "STREX_SPEC",
+        "PublicDescription": "Exclusive operation speculatively executed, STREX or STX"
+    },
+    {
+        "ArchStdEvent": "LD_SPEC",
+        "PublicDescription": "Operation speculatively executed, load"
+    },
+    {
+        "ArchStdEvent": "ST_SPEC",
+        "PublicDescription": "Operation speculatively executed, store"
+    },
+    {
+        "ArchStdEvent": "LDST_SPEC",
+        "PublicDescription": "Operation speculatively executed, load or store. This event counts the sum of LD_SPEC and ST_SPEC"
+    },
+    {
+        "ArchStdEvent": "DP_SPEC",
+        "PublicDescription": "Operation speculatively executed, integer data-processing"
+    },
+    {
+        "ArchStdEvent": "ASE_SPEC",
+        "PublicDescription": "Operation speculatively executed, Advanced SIMD instruction"
+    },
+    {
+        "ArchStdEvent": "VFP_SPEC",
+        "PublicDescription": "Operation speculatively executed, floating-point instruction"
+    },
+    {
+        "ArchStdEvent": "PC_WRITE_SPEC",
+        "PublicDescription": "Operation speculatively executed, software change of the PC"
+    },
+    {
+        "ArchStdEvent": "CRYPTO_SPEC",
+        "PublicDescription": "Operation speculatively executed, Cryptographic instruction"
+    },
+    {
+        "ArchStdEvent": "ISB_SPEC",
+        "PublicDescription": "Barrier speculatively executed, ISB"
+    },
+    {
+        "ArchStdEvent": "DSB_SPEC",
+        "PublicDescription": "Barrier speculatively executed, DSB"
+    },
+    {
+        "ArchStdEvent": "DMB_SPEC",
+        "PublicDescription": "Barrier speculatively executed, DMB"
+    },
+    {
+        "ArchStdEvent": "RC_LD_SPEC",
+        "PublicDescription": "Release consistency operation speculatively executed, load-acquire"
+    },
+    {
+        "ArchStdEvent": "RC_ST_SPEC",
+        "PublicDescription": "Release consistency operation speculatively executed, store-release"
+    },
+    {
+        "PublicDescription": "Instruction architecturally executed, Write to CID_EL0. The counter counts architecturally executed instructions which write to the Compartment ID Register",
+        "EventCode": "0x208",
+        "EventName": "CID_EL0_WRITE_RETIRED",
+        "BriefDescription": "Instruction architecturally executed, Write to CID_EL0. The counter counts architecturally executed instructions which write to the Compartment ID Register"
+    },
+    {
+        "PublicDescription": "Instruction architecturally executed, Write to DDC_ELx, RDDC_EL0. The counter counts architecturally executed instructions which write to any Default Data Capability",
+        "EventCode": "0x209",
+        "EventName": "DDC_WRITE_RETIRED",
+        "BriefDescription": "Instruction architecturally executed, Write to DDC_ELx, RDDC_EL0. The counter counts architecturally executed instructions which write to any Default Data Capability"
+    },
+    {
+        "PublicDescription": "Read from DDC_ELx, RDDC_EL0, Operations Speculatively Executed. The counter counts speculatively executed operations which read from any Default Data Capability",
+        "EventCode": "0x20A",
+        "EventName": "DDC_READ_SPEC",
+        "BriefDescription": "Read from DDC_ELx, RDDC_EL0, Operations Speculatively Executed. The counter counts speculatively executed operations which read from any Default Data Capability"
+    },
+    {
+        "PublicDescription": "Capability Load Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Capability load instructions",
+        "EventCode": "0x210",
+        "EventName": "CAP_LD_SPEC",
+        "BriefDescription": "Capability Load Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Capability load instructions"
+    },
+    {
+        "PublicDescription": "Capability Store Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Capability store instructions",
+        "EventCode": "0x211",
+        "EventName": "CAP_ST_SPEC",
+        "BriefDescription": "Capability Store Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Capability store instructions"
+    },
+    {
+        "PublicDescription": "Alternate Base Capability Load Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Alternate Base Capability load instructions",
+        "EventCode": "0x212",
+        "EventName": "CAP_ALT_LD_SPEC",
+        "BriefDescription": "Alternate Base Capability Load Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Alternate Base Capability load instructions"
+    },
+    {
+        "PublicDescription": "Alternate Base Capability Store Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Alternate Base Capability store instructions",
+        "EventCode": "0x213",
+        "EventName": "CAP_ALT_ST_SPEC",
+        "BriefDescription": "Alternate Base Capability Store Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Alternate Base Capability store instructions"
+    },
+    {
+        "PublicDescription": "Alternate Base Load Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Alternate Base load instructions",
+        "EventCode": "0x214",
+        "EventName": "ALT_LD_SPEC",
+        "BriefDescription": "Alternate Base Load Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Alternate Base load instructions"
+    },
+    {
+        "PublicDescription": "Alternate Base Store Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Alternate Base store instructions",
+        "EventCode": "0x215",
+        "EventName": "ALT_ST_SPEC",
+        "BriefDescription": "Alternate Base Store Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Alternate Base store instructions"
+    },
+    {
+        "PublicDescription": "LDCT Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Load Tags instructions",
+        "EventCode": "0x216",
+        "EventName": "LDCT_SPEC",
+        "BriefDescription": "LDCT Instructions, Operations Speculatively Executed. The counter counts speculatively executed operations due to Load Tags instructions"
+    },
+    {
+        "PublicDescription": "LDCT Instructions When Capability Tags are Zero, Operations Speculatively Executed. The counter counts speculatively executed operations due to Load Capability Tags instructions where the Capability Tags to be loaded are all zero",
+        "EventCode": "0x217",
+        "EventName": "LDCT_NO_CAP_SPEC",
+        "BriefDescription": "LDCT Instructions When Capability Tags are Zero, Operations Speculatively Executed. The counter counts speculatively executed operations due to Load Capability Tags instructions where the Capability Tags to be loaded are all zero"
+    }
+]
diff --git a/lib/libpmc/pmu-events/arch/arm64/arm/rainier/memory.json b/lib/libpmc/pmu-events/arch/arm64/arm/rainier/memory.json
@@ -0,0 +1,30 @@
+[
+    {
+        "ArchStdEvent": "MEM_ACCESS",
+        "PublicDescription": "Data memory access. This event counts memory accesses due to load or store instructions. The following instructions are not counted:\nInstruction fetches.\nCache maintenance instructions.\nTranslation table walks or prefetches. This event counts the sum of MEM_ACCESS_RD and MEM_ACCESS_WR"
+    },
+    {
+        "ArchStdEvent": "REMOTE_ACCESS",
+        "PublicDescription": "Access to another socket in a multi-socket system"
+    },
+    {
+        "ArchStdEvent": "MEM_ACCESS_RD",
+        "PublicDescription": "Data memory access, read. This event counts memory accesses due to load instructions. The following instructions are not counted:\nInstruction fetches.\nCache maintenance instructions.\nTranslation table walks.\nPrefetches"
+    },
+    {
+        "ArchStdEvent": "MEM_ACCESS_WR",
+        "PublicDescription": "Data memory access, write. This event counts memory accesses due to store instructions. The following instructions are not counted:\nInstruction fetches.\nCache maintenance instructions.\nTranslation table walks.\nPrefetches"
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_LD_SPEC",
+        "PublicDescription": "Unaligned access, read"
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_ST_SPEC",
+        "PublicDescription": "Unaligned access, write"
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_LDST_SPEC",
+        "PublicDescription": "Unaligned access"
+    }
+]