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Initial implementation of regalloc2. #1

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Sep 1, 2021
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8e923b0
Initial public commit of regalloc2.
cfallin Apr 13, 2021
33ac6cb
Heuristic improvement: reg-scan offset by inst location.
cfallin Apr 14, 2021
a08b012
Add support for reftypes/stackmaps and Stack constraints, and misc AP…
cfallin Apr 18, 2021
940c1b7
Changes from review comments.
cfallin Apr 18, 2021
34ab744
Add GitHub CI config.
cfallin Apr 18, 2021
414f3f8
Factored out test program and fuzzing features; core crate now only d…
cfallin Apr 18, 2021
49c54b6
Misc usability and functionality enhancements:
cfallin May 1, 2021
9e7021c
Derive Ord/hash on OperandOrAllocation.
cfallin May 4, 2021
15ed2d6
Allow multiple defs per vreg (i.e., accept non-SSA code).
cfallin May 6, 2021
48fbc23
BitVec::get() takes immutable self
cfallin May 6, 2021
ab828b6
MachineEnv fields are public
cfallin May 6, 2021
80cdd0c
Properly handle multiple same-fixed-reg constraints to the same vreg …
cfallin May 6, 2021
1a7a0c5
Some performance tweaks -- try to reduce register probe count with so…
cfallin May 6, 2021
747c56c
Some micro-optimizations in BitVec.
cfallin May 6, 2021
e2beb47
Handle moves specially with move-insertion logic rather than ordinary…
cfallin May 7, 2021
07a5a88
BitVec perf: use adaptive hybrid chunked small-array + FxHashMap.
cfallin May 7, 2021
02b6516
Some memory-size/bitpacking optimizations
cfallin May 7, 2021
a148dcc
Parameterize adaptive-map size in BitVec.
cfallin May 7, 2021
2ff02b5
Some perf opts in liveness computation and set impl:
cfallin May 7, 2021
2ba5185
Fuzzbugfix: actually do need eager liveness computation; must uphold …
cfallin May 7, 2021
42582e0
Some stats for loop effects on liveins: 487k loop set-unions (441 loo…
cfallin May 7, 2021
3713d61
Replace approximate liveness with true iterative liveness; turns out …
cfallin May 7, 2021
0f3454b
Inlining on btree commitment map comparators for a 10% win
cfallin May 7, 2021
3ddcf05
Optimizations: (i) range-summary array; (ii) early exit from btree pr…
cfallin May 8, 2021
4f63467
Pinned-VReg mechanism.
cfallin May 8, 2021
df59b5e
Inline all the things (ProgPoint edition)
cfallin May 8, 2021
a453501
sort_unstable (quicksort) everywhere
cfallin May 8, 2021
bfe1c63
Some preallocation and removal of one u32 from LiveRange struct
cfallin May 8, 2021
040c3c8
Some structure packing: Use now fits in three u32s.
cfallin May 8, 2021
d2cc4f1
More efficient queue_bundles (saves 18% on clang.wasm)
cfallin May 8, 2021
a6e3128
Support `mod` (modify) operands, for better efficiency with regalloc.…
cfallin May 8, 2021
4185eab
More efficient live-range creation re: uses
cfallin May 8, 2021
e41b010
Struct-of-array transform: pull LiveRangeHot out of LiveRange with ju…
cfallin May 8, 2021
ed339ab
Some minor opts: inlining, and smallvec reuse
cfallin May 8, 2021
179ef0e
Bugfix: Mod with dead def spans both Before and After positions
cfallin May 8, 2021
3d0d760
Bugfix: process parallel moves separately for Int and Float classes
cfallin May 8, 2021
00c64f6
Handle moves by joining LRs at inst boundary, not middle of move inst
cfallin May 9, 2021
f1fc9a8
Fix related to move handling
cfallin May 9, 2021
b9e8988
Error checking: properly signal a crit-edge requirement failure (used…
cfallin May 9, 2021
095a883
Fix crit-edge detection logic in CFGInfo analysis
cfallin May 9, 2021
509c5dc
Remove sanity-check logic in range summary construction -- zero-length
cfallin May 9, 2021
9fdc69e
fuzzbug fix in range-summary iter
cfallin May 9, 2021
c380b0d
assert fix: RegClass doesn't need to match for spillslots (can be reu…
cfallin May 9, 2021
8d7530d
Edge moves always before jumps, never after; semantics are too subtle…
cfallin May 9, 2021
34421fc
fix to prog-move handling: happens in middle of inst; and insert uses…
cfallin May 9, 2021
5c5ea4c
bugfix
cfallin May 9, 2021
4f26b1c
Properly handle prog-moves with fixed srcs or dests
cfallin May 9, 2021
b7fd53e
Fix checker: after moving edge-moves to prior to last branch of block…
cfallin May 10, 2021
0dbf4a7
Collect full conflict-bundle list, by not ending PhysReg probe on fir…
cfallin May 10, 2021
f7551c6
Integrate prog-moves with LR-moves; this should in theory reduce move…
cfallin May 11, 2021
e1a37cf
some more stats
cfallin May 11, 2021
b069ae0
Use hot-code map to augment spill weights of each use
cfallin May 12, 2021
6066d02
More annotations
cfallin May 12, 2021
37fa3ec
Improve prog-move handling: no use/def records, just directly connect…
cfallin May 12, 2021
1f9258b
Detect undefined liveins.
cfallin May 12, 2021
5b55948
Check branch-args for conflicts with edge-move placement.
cfallin May 14, 2021
f0fbf3a
Rework data structures: bundles have a SmallVec of ranges, and ranges…
cfallin May 18, 2021
328c900
fuzzbug fixes
cfallin May 18, 2021
8e0d0f1
fuzzbug fix
cfallin May 18, 2021
4389f16
debugging log message for liveins
cfallin May 18, 2021
c3513b9
Bugfix: don't do a split-at-intermediate-defs split if the first such…
cfallin May 18, 2021
04c8e46
Only do annotations in debug builds
cfallin May 19, 2021
e1f67e8
Pinned VRegs for use with regalloc.rs shim to support RealRegs.
cfallin May 19, 2021
f1c6dfe
Optionally show annotations in final allocation/program dump based on…
cfallin May 19, 2021
f56676f
Fixed all fuzzer targets (some API changes)
cfallin May 20, 2021
ce935c1
Add all empty LRs to a single "spill bundle", to avoid many small bun…
cfallin May 20, 2021
f0b24cf
Remove all-empty-ranges-to-spill-bundle: prioritizing same-alloc for …
cfallin May 20, 2021
2a5f571
WIP: Handle moves between realregs (pregs) and vregs somewhat special…
cfallin May 21, 2021
ec7fdeb
Properly handle RReg-RReg moves in new scheme
cfallin May 21, 2021
466ea2c
Simpler / possibly better splitting: split based on conflict position…
cfallin May 21, 2021
4b46c63
Fuzzbug fixes for simpler splitting
cfallin May 22, 2021
4696691
Another fuzzbug fix: proper checker-hint ordering when V-R and V-V mo…
cfallin May 22, 2021
a6c89b1
Avoid O(n^2) in liverange construction: we always build LRs in (rever…
cfallin May 22, 2021
107c091
Simple speedup in bundle merge: set bundle while everything is in cac…
cfallin May 22, 2021
59967ff
TODO-list update: braindump of next ideas to work on.
cfallin May 24, 2021
46feacc
Fuzzbug fix: don't merge bundles that have conflicting requirements. …
cfallin May 24, 2021
78c0091
Fuzzbug fix re: new requirements computation and multi-fixed-reg fixup.
cfallin May 24, 2021
10d9265
avoid some redundant work by computing initial reqs only once
cfallin May 24, 2021
5120681
Fuzzbug fix for requirement recomputation on minimal bundles with mul…
cfallin May 25, 2021
5895ae8
Remove precomputed requirements from ranges and bundles; cost of stru…
cfallin May 25, 2021
5b47462
Loop depth instead of hot/cold, with fast O(n) loop-depth computation…
cfallin May 25, 2021
3382f9a
Split based on first conflict of lowest-weight conflict, not first co…
cfallin May 25, 2021
8887077
small fix: preserve starts-at-def flag when setting liverange weight
cfallin May 25, 2021
7cdcb20
Split heuristic: split before entering deeper loop nest
cfallin May 25, 2021
ca5f24f
Hint the same PReg for both halves of a split
cfallin May 25, 2021
b3dc2b2
Alloc spillsets for whole vreg, not just spilled LRs. This is a prere…
cfallin May 26, 2021
4e0dd1f
little tweak to avoid a div/mod on every iter of a PReg alloc loop
cfallin May 26, 2021
dcf6f47
inline some things
cfallin May 26, 2021
e521811
Avoid re-spilling to spillslot when still clean: intra-block edition …
cfallin May 27, 2021
13bde99
bugfix with clean-spill opt: avoid if liverange starts at start of bl…
cfallin May 27, 2021
7171624
Don't generate r1->scratch,scratch-r1 sequence for cyclic moves of r1…
cfallin May 27, 2021
43d7095
Properly split when we hit a fixed conflict
cfallin May 28, 2021
789651f
Rework inner allocation-loop code: choose more wisely between splitti…
cfallin May 29, 2021
f49167e
emit annotations at Info level, for easier selective perf-debugging
cfallin May 29, 2021
44ca189
Fuzzbug fix: properly check for conflicting reqs before merging bundl…
cfallin Jun 1, 2021
e49727d
Fuzzbug fix: fix some weirdness with BTree iteration inner loop
cfallin Jun 1, 2021
2614eac
fuzzbug fix: restore clean error exit required by regalloc.rs fuzzer …
cfallin Jun 1, 2021
a2a770e
Fuzzbug fix
cfallin Jun 2, 2021
2fe276c
BTreeMap probe fix (fuzzbug): BTree does not interact nicely with Liv…
cfallin Jun 2, 2021
dc2b0d1
Add a perf idea to TODO list
cfallin Jun 2, 2021
6a0739b
Implement spill-bundle: move all empty ranges, and empty leading/trai…
cfallin Jun 3, 2021
00e4240
merge bundles much faster by just concatenating range-lists and unsta…
cfallin Jun 4, 2021
5560499
Adaptive commitment-map scanning: re-probe from root if we skip too m…
cfallin Jun 4, 2021
30f42a8
Fix fuzzbug: properly detect too-many-live-regs condition on fuzzing …
cfallin Jun 4, 2021
0eaa0fd
Fix to checker: analyze all blocks, even if out-state of entry block …
cfallin Jun 5, 2021
2be7bdb
Split-at-first-conflict: first conflict is first of (start of our ran…
cfallin Jun 7, 2021
c6bcd3c
WIP: redundant-move elimination.
cfallin Jun 8, 2021
940bc40
Redundant move eliminator.
cfallin Jun 8, 2021
0f270e5
WIP.
cfallin Jun 8, 2021
e33790d
do not remove redundant move if we don't have local (within-basic-blo…
cfallin Jun 8, 2021
f898b8d
Some fuzzbug fixes
cfallin Jun 10, 2021
2851ac8
Working redundant-move elimination
cfallin Jun 10, 2021
4ba7b2f
Improve redundant-move elimination: don't skip the case where we don'…
cfallin Jun 10, 2021
fcbf384
Use hashset to avoid linear scan in conflict-bundle-set deduplication
cfallin Jun 10, 2021
09b2dd4
TODO list update
cfallin Jun 11, 2021
1bd1248
Avoid stack-to-stack moves by allocating an extra spillslot and re-us…
cfallin Jun 11, 2021
ea81422
Update TODO list
cfallin Jun 11, 2021
a686d5a
Always recompute prio when recomputing bundle properties; otherwise i…
cfallin Jun 11, 2021
6ec6207
Add design document.
cfallin Jun 18, 2021
6944bc4
Fix typo (thanks @bjorn3).
cfallin Jun 18, 2021
b36a563
Cleanup: split allocator implemntation into 11 files of more reasonab…
cfallin Jun 18, 2021
36975b8
Add doc-comment note on Edit that stack-to-stack moves are never gene…
cfallin Jun 19, 2021
caf7274
Remove unused pred_pos
cfallin Jun 19, 2021
50eb6fc
Keep internal modules private, but re-export under fuzzing feature flag
cfallin Jun 19, 2021
736f636
Add fixed-non-allocatable operand support.
cfallin Jun 19, 2021
22eed0a
Make bitvec public; it is used by regalloc.rs shim too.
cfallin Jun 19, 2021
a58d36f
TODO update: make note on idea for large-input support
cfallin Jun 19, 2021
21fb233
reduce nesting level in DESIGN.md to make pandoc-to-pdf happy
cfallin Jun 19, 2021
245c212
Revert "Add fixed-non-allocatable operand support."
cfallin Jun 21, 2021
f27abc9
Remove infinite-loop check: it is not a high enough bound in some pat…
cfallin Jun 22, 2021
66d6821
Fix perf issue with many safepoints.
cfallin Jun 22, 2021
4c193a9
Fix heuristic-cost function overflow with high loop depth (found by @…
cfallin Jul 28, 2021
c9e8a87
Update TODO with new items from private feedback from @julian-seward1.
cfallin Aug 12, 2021
84285c2
Rename OperandPolicy to OperandConstraint as per feedback from @julia…
cfallin Aug 12, 2021
a591535
Use "vector" or "sequence" in lieu of "list" in DESIGN.md, except whe…
cfallin Aug 12, 2021
0c79584
Add some more detail about spill bundles to design doc.
cfallin Aug 12, 2021
38323e0
Some more design-doc and TODO updates from @julian-seward1's feedback.
cfallin Aug 12, 2021
3e1e0f3
Convert all log::debug to log::trace.
cfallin Aug 12, 2021
1f30958
Improve domtree as per @Amanieu's feedback.
cfallin Aug 12, 2021
b76b774
Fix comment in postorder.rs.
cfallin Aug 12, 2021
2f85643
Review feedback.
cfallin Aug 12, 2021
7652b4b
Review feedback.
cfallin Aug 12, 2021
82b7e6b
Review feedback: bitvec: struct-like enum variants, and factor out on…
cfallin Aug 12, 2021
eaf8647
BitVec: remove zero words to avoid expanding when unnecessary.
cfallin Aug 12, 2021
c071e44
Derive PartialOrd/Ord/Hash for Operand.
cfallin Aug 12, 2021
ffc06b2
Debug output for Operands: omit default/most common positions.
cfallin Aug 12, 2021
f1a989f
Add malloc/free optimization to TODO
cfallin Aug 12, 2021
8ed83e3
Fix `BitVec::get_or_insert` to scan only once.
cfallin Aug 12, 2021
69ad31f
Replace remaining instances of use of `debug` feature with `debug_ass…
cfallin Aug 13, 2021
e10bffb
Fix bug in refactored BitVec (found by @Amanieu).
cfallin Aug 14, 2021
6d313f2
Address review comments: more doc comments and some minor refactorings.
cfallin Aug 31, 2021
3a18564
Addressed more review comments.
cfallin Aug 31, 2021
b19fa48
Rename operand positions to Early and Late, and make weights f16/f32 …
cfallin Sep 1, 2021
6389071
Address review comments.
cfallin Sep 1, 2021
6f0893d
Address review comments.
cfallin Sep 1, 2021
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21 changes: 11 additions & 10 deletions src/cfg.rs
Original file line number Diff line number Diff line change
Expand Up @@ -38,23 +38,24 @@ pub struct CFGInfo {

impl CFGInfo {
pub fn new<F: Function>(f: &F) -> Result<CFGInfo, RegAllocError> {
let postorder =
postorder::calculate(f.blocks(), f.entry_block(), |block| f.block_succs(block));
let postorder = postorder::calculate(f.num_blocks(), f.entry_block(), |block| {
f.block_succs(block)
});
let domtree = domtree::calculate(
f.blocks(),
f.num_blocks(),
|block| f.block_preds(block),
&postorder[..],
f.entry_block(),
);
let mut insn_block = vec![Block::invalid(); f.insts()];
let mut insn_block = vec![Block::invalid(); f.num_insts()];
let mut vreg_def_inst = vec![Inst::invalid(); f.num_vregs()];
let mut vreg_def_blockparam = vec![(Block::invalid(), 0); f.num_vregs()];
let mut block_entry = vec![ProgPoint::before(Inst::invalid()); f.blocks()];
let mut block_exit = vec![ProgPoint::before(Inst::invalid()); f.blocks()];
let mut backedge_in = vec![0; f.blocks()];
let mut backedge_out = vec![0; f.blocks()];
let mut block_entry = vec![ProgPoint::before(Inst::invalid()); f.num_blocks()];
let mut block_exit = vec![ProgPoint::before(Inst::invalid()); f.num_blocks()];
let mut backedge_in = vec![0; f.num_blocks()];
let mut backedge_out = vec![0; f.num_blocks()];

for block in 0..f.blocks() {
for block in 0..f.num_blocks() {
let block = Block::new(block);
for (i, param) in f.block_params(block).iter().enumerate() {
vreg_def_blockparam[param.vreg()] = (block, i as u32);
Expand Down Expand Up @@ -116,7 +117,7 @@ impl CFGInfo {
let mut approx_loop_depth = vec![];
let mut backedge_stack: SmallVec<[usize; 4]> = smallvec![];
let mut cur_depth = 0;
for block in 0..f.blocks() {
for block in 0..f.num_blocks() {
if backedge_in[block] > 0 {
cur_depth += 1;
backedge_stack.push(backedge_in[block]);
Expand Down
49 changes: 4 additions & 45 deletions src/checker.rs
Original file line number Diff line number Diff line change
Expand Up @@ -389,17 +389,6 @@ impl CheckerState {
self.allocations.remove(&Allocation::reg(*clobber));
}
}
&CheckerInst::BlockParams {
ref vregs,
ref allocs,
..
} => {
for (vreg, alloc) in vregs.iter().zip(allocs.iter()) {
let reftyped = checker.reftyped_vregs.contains(vreg);
self.allocations
.insert(*alloc, CheckerValue::Reg(*vreg, reftyped));
}
}
&CheckerInst::DefAlloc { alloc, vreg } => {
let reftyped = checker.reftyped_vregs.contains(&vreg);
self.allocations
Expand Down Expand Up @@ -478,14 +467,6 @@ pub(crate) enum CheckerInst {
clobbers: Vec<PReg>,
},

/// The top of a block with blockparams. We define the given vregs
/// into the given allocations.
BlockParams {
block: Block,
vregs: Vec<VReg>,
allocs: Vec<Allocation>,
},

/// Define an allocation's contents. Like BlockParams but for one
/// allocation. Used sometimes when moves are elided but ownership
/// of a value is logically transferred to a new vreg.
Expand Down Expand Up @@ -514,7 +495,7 @@ impl<'a, F: Function> Checker<'a, F> {
let mut bb_insts = HashMap::new();
let mut reftyped_vregs = HashSet::new();

for block in 0..f.blocks() {
for block in 0..f.num_blocks() {
let block = Block::new(block);
bb_in.insert(block, Default::default());
bb_insts.insert(block, vec![]);
Expand Down Expand Up @@ -548,7 +529,7 @@ impl<'a, F: Function> Checker<'a, F> {
// For each original instruction, create an `Op`.
let mut last_inst = None;
let mut insert_idx = 0;
for block in 0..self.f.blocks() {
for block in 0..self.f.num_blocks() {
let block = Block::new(block);
for inst in self.f.block_insns(block).iter() {
assert!(last_inst.is_none() || inst > last_inst.unwrap());
Expand Down Expand Up @@ -617,17 +598,6 @@ impl<'a, F: Function> Checker<'a, F> {
.unwrap()
.push(CheckerInst::DefAlloc { alloc, vreg });
}
&Edit::BlockParams {
ref vregs,
ref allocs,
} => {
let inst = CheckerInst::BlockParams {
block,
vregs: vregs.clone(),
allocs: allocs.clone(),
};
self.bb_insts.get_mut(&block).unwrap().push(inst);
}
}
}
}
Expand All @@ -636,7 +606,7 @@ impl<'a, F: Function> Checker<'a, F> {
fn analyze(&mut self) {
let mut queue = VecDeque::new();
let mut queue_set = HashSet::new();
for block in 0..self.f.blocks() {
for block in 0..self.f.num_blocks() {
let block = Block::new(block);
queue.push_back(block);
queue_set.insert(block);
Expand Down Expand Up @@ -718,7 +688,7 @@ impl<'a, F: Function> Checker<'a, F> {
for vreg in self.f.reftype_vregs() {
log::trace!(" REF: {}", vreg);
}
for bb in 0..self.f.blocks() {
for bb in 0..self.f.num_blocks() {
let bb = Block::new(bb);
log::trace!("block{}:", bb.index());
let insts = self.bb_insts.get(&bb).unwrap();
Expand All @@ -743,17 +713,6 @@ impl<'a, F: Function> Checker<'a, F> {
&CheckerInst::Move { from, into } => {
log::trace!(" {} -> {}", from, into);
}
&CheckerInst::BlockParams {
ref vregs,
ref allocs,
..
} => {
let mut args = vec![];
for (vreg, alloc) in vregs.iter().zip(allocs.iter()) {
args.push(format!("{}:{}", vreg, alloc));
}
log::trace!(" blockparams: {}", args.join(", "));
}
&CheckerInst::DefAlloc { alloc, vreg } => {
log::trace!(" defalloc: {}:{}", vreg, alloc);
}
Expand Down
4 changes: 2 additions & 2 deletions src/fuzzing/func.rs
Original file line number Diff line number Diff line change
Expand Up @@ -75,11 +75,11 @@ pub struct Func {
}

impl Function for Func {
fn insts(&self) -> usize {
fn num_insts(&self) -> usize {
self.insts.len()
}

fn blocks(&self) -> usize {
fn num_blocks(&self) -> usize {
self.blocks.len()
}

Expand Down
2 changes: 1 addition & 1 deletion src/ion/dump.rs
Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@ impl<'a, F: Function> Env<'a, F> {

pub fn dump_results(&self) {
log::info!("=== REGALLOC RESULTS ===");
for block in 0..self.func.blocks() {
for block in 0..self.func.num_blocks() {
let block = Block::new(block);
log::info!(
"block{}: [succs {:?} preds {:?}]",
Expand Down
6 changes: 3 additions & 3 deletions src/ion/liveranges.rs
Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,7 @@ impl<'a, F: Function> Env<'a, F> {
self.vregs[v.vreg()].is_pinned = true;
}
// Create allocations too.
for inst in 0..self.func.insts() {
for inst in 0..self.func.num_insts() {
let start = self.allocs.len() as u32;
self.inst_alloc_offsets.push(start);
for _ in 0..self.func.inst_operands(Inst::new(inst)).len() {
Expand Down Expand Up @@ -247,7 +247,7 @@ impl<'a, F: Function> Env<'a, F> {

pub fn compute_liveness(&mut self) -> Result<(), RegAllocError> {
// Create initial LiveIn and LiveOut bitsets.
for _ in 0..self.func.blocks() {
for _ in 0..self.func.num_blocks() {
self.liveins.push(BitVec::new());
self.liveouts.push(BitVec::new());
}
Expand Down Expand Up @@ -347,7 +347,7 @@ impl<'a, F: Function> Env<'a, F> {
let mut vreg_ranges: Vec<LiveRangeIndex> =
vec![LiveRangeIndex::invalid(); self.func.num_vregs()];

for i in (0..self.func.blocks()).rev() {
for i in (0..self.func.num_blocks()).rev() {
let block = Block::new(i);

self.stats.livein_blocks += 1;
Expand Down
2 changes: 1 addition & 1 deletion src/ion/merge.rs
Original file line number Diff line number Diff line change
Expand Up @@ -303,7 +303,7 @@ impl<'a, F: Function> Env<'a, F> {
self.bundles[bundle.index()].spillset = ssidx;
}

for inst in 0..self.func.insts() {
for inst in 0..self.func.num_insts() {
let inst = Inst::new(inst);

// Attempt to merge Reuse-constraint operand outputs with the
Expand Down
6 changes: 3 additions & 3 deletions src/ion/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -44,14 +44,14 @@ impl<'a, F: Function> Env<'a, F> {
cfginfo: CFGInfo,
annotations_enabled: bool,
) -> Self {
let n = func.insts();
let n = func.num_insts();
Self {
func,
env,
cfginfo,

liveins: Vec::with_capacity(func.blocks()),
liveouts: Vec::with_capacity(func.blocks()),
liveins: Vec::with_capacity(func.num_blocks()),
liveouts: Vec::with_capacity(func.num_blocks()),
blockparam_outs: vec![],
blockparam_ins: vec![],
blockparam_allocs: vec![],
Expand Down
27 changes: 11 additions & 16 deletions src/ion/moves.rs
Original file line number Diff line number Diff line change
Expand Up @@ -166,8 +166,8 @@ impl<'a, F: Function> Env<'a, F> {
}
}

let mut half_moves: Vec<HalfMove> = Vec::with_capacity(6 * self.func.insts());
let mut reuse_input_insts = Vec::with_capacity(self.func.insts() / 2);
let mut half_moves: Vec<HalfMove> = Vec::with_capacity(6 * self.func.num_insts());
let mut reuse_input_insts = Vec::with_capacity(self.func.num_insts() / 2);

let mut blockparam_in_idx = 0;
let mut blockparam_out_idx = 0;
Expand Down Expand Up @@ -290,7 +290,7 @@ impl<'a, F: Function> Env<'a, F> {
// same allocation) and if the vreg is live, add a
// Source half-move.
let mut block = self.cfginfo.insn_block[range.from.inst().index()];
while block.is_valid() && block.index() < self.func.blocks() {
while block.is_valid() && block.index() < self.func.num_blocks() {
if range.to < self.cfginfo.block_exit[block.index()].next() {
break;
}
Expand Down Expand Up @@ -376,7 +376,7 @@ impl<'a, F: Function> Env<'a, F> {
if self.cfginfo.block_entry[block.index()] < range.from {
block = block.next();
}
while block.is_valid() && block.index() < self.func.blocks() {
while block.is_valid() && block.index() < self.func.num_blocks() {
if self.cfginfo.block_entry[block.index()] >= range.to {
break;
}
Expand Down Expand Up @@ -1114,11 +1114,13 @@ impl<'a, F: Function> Env<'a, F> {
.collect::<Vec<_>>();
assert_eq!(vregs.len(), self.func.block_params(block).len());
assert_eq!(allocs.len(), self.func.block_params(block).len());
self.add_edit(
self.cfginfo.block_entry[block.index()],
InsertMovePrio::BlockParam,
Edit::BlockParams { vregs, allocs },
);
for (vreg, alloc) in vregs.into_iter().zip(allocs.into_iter()) {
self.add_edit(
self.cfginfo.block_entry[block.index()],
InsertMovePrio::BlockParam,
Edit::DefAlloc { alloc, vreg },
);
}
}

// Ensure edits are in sorted ProgPoint order. N.B.: this must
Expand All @@ -1139,13 +1141,6 @@ impl<'a, F: Function> Env<'a, F> {
format!("move {} -> {} ({:?})", from, to, to_vreg),
);
}
&Edit::BlockParams {
ref vregs,
ref allocs,
} => {
let s = format!("blockparams vregs:{:?} allocs:{:?}", vregs, allocs);
self.annotate(ProgPoint::from_index(pos), s);
}
&Edit::DefAlloc { alloc, vreg } => {
let s = format!("defalloc {:?} := {:?}", alloc, vreg);
self.annotate(ProgPoint::from_index(pos), s);
Expand Down
2 changes: 1 addition & 1 deletion src/ion/process.rs
Original file line number Diff line number Diff line change
Expand Up @@ -798,7 +798,7 @@ impl<'a, F: Function> Env<'a, F> {
loop {
attempts += 1;
log::trace!("attempt {}, req {:?}", attempts, req);
debug_assert!(attempts < 100 * self.func.insts());
debug_assert!(attempts < 100 * self.func.num_insts());

let (class, fixed_preg) = match req {
Requirement::Fixed(preg) => (preg.class(), Some(preg)),
Expand Down
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