aot: implement a few more relocation types for riscv #2318
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Lightly tested on qemu riscv64.
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this partly fixes #2312 |
wenyongh
reviewed
Jun 27, 2023
| @@ -9,6 +9,8 @@ | |||
| #define R_RISCV_64 2 | |||
| #define R_RISCV_CALL 18 | |||
| #define R_RISCV_CALL_PLT 19 | |||
| #define R_RISCV_PCREL_HI20 23 | |||
| #define R_RISCV_PCREL_LO12_I 24 | |||
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Should we also implement R_RISCV_PCREL_LO12_S (25)? We had implemented R_RISCV_LO12_S, the similar change can be applied to case R_RISCV_LO12_S, like the change to case R_RISCV_LO12_I.
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maybe. but i'm not sure how i can test it.
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OK, let's merge this PR first, and implement R_RISCV_PCREL_LO12_S in the future if needed.
victoryang00
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to victoryang00/wamr-aot-gc-checkpoint-restore
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May 27, 2024
…e#2318) This PR partly fixes bytecodealliance#2312. Lightly tested on qemu riscv64.
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Lightly tested on qemu riscv64.