Enable spectest on riscv64 #2843
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| else { | ||
| val = (int32)((intptr_t)symbol_addr + (intptr_t)reloc_addend); | ||
| } | ||
| /* Already handled in R_RISCV_PCREL_HI20 */ |
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R_RISCV_PCREL_HI20 doesn't equal to R_RISCV_PCREL_LO12_I, why not need to handle R_RISCV_PCREL_LO12_I here?
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This is a little trick to reuse the code for both R_RISCV_CALL/R_RISCV_CALL_PLT/R_RISCV_PCREL_HI20, R_RISCV_PCREL_LO12_I handled in line 373.
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But this branch only break, it does nothing, it is really strange. Should we add case R_RISCV_PCREL_LO12_I after case R_RISCV_PCREL_HI20 to reuse the code, and then update some code in that handling accordingly?
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Essential check added here
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
spec_test_on_nuttx.yml
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
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Latest spec test here: https://github.com/no1wudi/wasm-micro-runtime/actions/runs/7081980946 |
Fix relocation issues on riscv and update test scripts and CI to enable test spec cases on riscv QEMU.
Test result : https://github.com/no1wudi/wasm-micro-runtime/actions/runs/7055453059