x64: refactor EVEX encodings to use EvexInstruction

This change replaces the `encode_evex` function with a builder-style struct, `EvexInstruction`. This approach clarifies the code, adds documentation, and results in slight speedups when benchmarked.
bytecodealliance · Apr 13, 2021 · 377253b · 377253b
1 parent 77602f9
commit 377253b
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Showing 4 changed files with 365 additions and 87 deletions.
diff --git a/cranelift/codegen/src/isa/x64/inst/emit.rs b/cranelift/codegen/src/isa/x64/inst/emit.rs
@@ -6,11 +6,11 @@ use crate::isa::x64::inst::args::*;
 use crate::isa::x64::inst::*;
 use crate::machinst::{inst_common, MachBuffer, MachInstEmit, MachLabel};
 use core::convert::TryInto;
-use cranelift_codegen_shared::isa::x86::EncodingBits;
-use encoding::evex::{encode_evex, EvexContext, EvexMasking};
+use encoding::evex::{EvexInstruction, EvexVectorLength};
 use encoding::rex::{
     emit_simm, emit_std_enc_enc, emit_std_enc_mem, emit_std_reg_mem, emit_std_reg_reg, int_reg_enc,
-    low8_will_sign_extend_to_32, low8_will_sign_extend_to_64, reg_enc, LegacyPrefixes, RexFlags,
+    low8_will_sign_extend_to_32, low8_will_sign_extend_to_64, reg_enc, LegacyPrefixes, OpcodeMap,
+    RexFlags,
 };
 use log::debug;
 use regalloc::{Reg, Writable};
@@ -1412,21 +1412,21 @@ pub(crate) fn emit(
         }
 
         Inst::XmmUnaryRmREvex { op, src, dst } => {
-            let bits = match op {
-                &Avx512Opcode::Vpabsq => EncodingBits::new(&[0x66, 0x0f, 0x38, 0x1f], 0, 1),
+            let opcode = match op {
+                Avx512Opcode::Vpabsq => 0x1f,
             };
             match src {
-                RegMem::Reg { reg: src } => encode_evex(
-                    bits,
-                    dst.to_reg().get_hw_encoding(),
-                    0,
-                    src.get_hw_encoding(),
-                    EvexContext::v128(),
-                    EvexMasking::default(),
-                    sink,
-                ),
+                RegMem::Reg { reg: src } => EvexInstruction::new()
+                    .length(EvexVectorLength::V128)
+                    .prefix(LegacyPrefixes::_66)
+                    .map(OpcodeMap::_0F38)
+                    .w(true)
+                    .opcode(opcode)
+                    .reg(dst.to_reg().get_hw_encoding())
+                    .rm(src.get_hw_encoding())
+                    .encode(sink),
                 _ => todo!(),
-            }
+            };
         }
 
         Inst::XmmRmR {