Add simd_extmul_* support for x64

build.rs

@@ -190,12 +190,9 @@ fn x64_should_panic(testsuite: &str, testname: &str, strategy: &str) -> bool {
 
  match (testsuite, testname) {
  ("simd", "simd_i16x8_extadd_pairwise_i8x16") => return true,
- ("simd", "simd_i16x8_extmul_i8x16") => return true,
  ("simd", "simd_i16x8_q15mulr_sat_s") => return true,
  ("simd", "simd_i32x4_extadd_pairwise_i16x8") => return true,
- ("simd", "simd_i32x4_extmul_i16x8") => return true,
  ("simd", "simd_i32x4_trunc_sat_f64x2") => return true,
- ("simd", "simd_i64x2_extmul_i32x4") => return true,
  ("simd", "simd_int_to_int_extend") => return true,
  ("simd", _) => return false,
  _ => {}
@@ -229,10 +226,7 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
  // These are new instructions that are not really implemented in any backend.
  ("simd", "simd_conversions")
  | ("simd", "simd_i16x8_extadd_pairwise_i8x16")
- | ("simd", "simd_i16x8_extmul_i8x16")
- | ("simd", "simd_i32x4_extadd_pairwise_i16x8")
- | ("simd", "simd_i32x4_extmul_i16x8")
- | ("simd", "simd_i64x2_extmul_i32x4") => return true,
+ | ("simd", "simd_i32x4_extadd_pairwise_i16x8") => return true,
 
  _ => {}
  },

cranelift/codegen/src/isa/x64/inst/args.rs

@@ -593,6 +593,9 @@ pub enum SseOpcode {
  Pmovzxwd,
  Pmovzxwq,
  Pmovzxdq,
+ Pmuldq,
+ Pmulhw,
+ Pmulhuw,
  Pmulld,
  Pmullw,
  Pmuludq,
@@ -617,7 +620,9 @@ pub enum SseOpcode {
  Psubusw,
  Ptest,
  Punpckhbw,
+ Punpckhwd,
  Punpcklbw,
+ Punpcklwd,
  Pxor,
  Rcpss,
  Roundps,
@@ -742,6 +747,8 @@ impl SseOpcode {
  | SseOpcode::Pminsw
  | SseOpcode::Pminub
  | SseOpcode::Pmovmskb
+ | SseOpcode::Pmulhw
+ | SseOpcode::Pmulhuw
  | SseOpcode::Pmullw
  | SseOpcode::Pmuludq
  | SseOpcode::Por
@@ -763,7 +770,9 @@ impl SseOpcode {
  | SseOpcode::Psubusb
  | SseOpcode::Psubusw
  | SseOpcode::Punpckhbw
+ | SseOpcode::Punpckhwd
  | SseOpcode::Punpcklbw
+ | SseOpcode::Punpcklwd
  | SseOpcode::Pxor
  | SseOpcode::Sqrtpd
  | SseOpcode::Sqrtsd
@@ -808,6 +817,7 @@ impl SseOpcode {
  | SseOpcode::Pmovzxwd
  | SseOpcode::Pmovzxwq
  | SseOpcode::Pmovzxdq
+ | SseOpcode::Pmuldq
  | SseOpcode::Pmulld
  | SseOpcode::Ptest
  | SseOpcode::Roundps
@@ -953,6 +963,9 @@ impl fmt::Debug for SseOpcode {
  SseOpcode::Pmovzxwd => "pmovzxwd",
  SseOpcode::Pmovzxwq => "pmovzxwq",
  SseOpcode::Pmovzxdq => "pmovzxdq",
+ SseOpcode::Pmuldq => "pmuldq",
+ SseOpcode::Pmulhw => "pmulhw",
+ SseOpcode::Pmulhuw => "pmulhuw",
  SseOpcode::Pmulld => "pmulld",
  SseOpcode::Pmullw => "pmullw",
  SseOpcode::Pmuludq => "pmuludq",
@@ -977,7 +990,9 @@ impl fmt::Debug for SseOpcode {
  SseOpcode::Psubusw => "psubusw",
  SseOpcode::Ptest => "ptest",
  SseOpcode::Punpckhbw => "punpckhbw",
+ SseOpcode::Punpckhwd => "punpckhwd",
  SseOpcode::Punpcklbw => "punpcklbw",
+ SseOpcode::Punpcklwd => "punpcklwd",
  SseOpcode::Pxor => "pxor",
  SseOpcode::Rcpss => "rcpss",
  SseOpcode::Roundps => "roundps",

cranelift/codegen/src/isa/x64/inst/emit.rs

@@ -1509,6 +1509,9 @@ pub(crate) fn emit(
  SseOpcode::Pminub => (LegacyPrefixes::_66, 0x0FDA, 2),
  SseOpcode::Pminuw => (LegacyPrefixes::_66, 0x0F383A, 3),
  SseOpcode::Pminud => (LegacyPrefixes::_66, 0x0F383B, 3),
+ SseOpcode::Pmuldq => (LegacyPrefixes::_66, 0x0F3828, 3),
+ SseOpcode::Pmulhw => (LegacyPrefixes::_66, 0x0FE5, 2),
+ SseOpcode::Pmulhuw => (LegacyPrefixes::_66, 0x0FE4, 2),
  SseOpcode::Pmulld => (LegacyPrefixes::_66, 0x0F3840, 3),
  SseOpcode::Pmullw => (LegacyPrefixes::_66, 0x0FD5, 2),
  SseOpcode::Pmuludq => (LegacyPrefixes::_66, 0x0FF4, 2),
@@ -1523,7 +1526,9 @@ pub(crate) fn emit(
  SseOpcode::Psubusb => (LegacyPrefixes::_66, 0x0FD8, 2),
  SseOpcode::Psubusw => (LegacyPrefixes::_66, 0x0FD9, 2),
  SseOpcode::Punpckhbw => (LegacyPrefixes::_66, 0x0F68, 2),
+ SseOpcode::Punpckhwd => (LegacyPrefixes::_66, 0x0F69, 2),
  SseOpcode::Punpcklbw => (LegacyPrefixes::_66, 0x0F60, 2),
+ SseOpcode::Punpcklwd => (LegacyPrefixes::_66, 0x0F61, 2),
  SseOpcode::Pxor => (LegacyPrefixes::_66, 0x0FEF, 2),
  SseOpcode::Subps => (LegacyPrefixes::None, 0x0F5C, 2),
  SseOpcode::Subpd => (LegacyPrefixes::_66, 0x0F5C, 2),