x64 new backend: port ABI implementation to shared infrastructure wit…

…h AArch64.

Previously, in #2128, we factored out a common "vanilla 64-bit ABI"
implementation from the AArch64 ABI code, with the idea that this should
be largely compatible with x64. This PR alters the new x64 backend to
make use of the shared infrastructure, removing the duplication that
existed previously. The generated code is nearly (not exactly) the same;
the only difference relates to how the clobber-save region is padded in
the prologue.

This also changes some register allocations in the aarch64 code because
call support in the shared ABI infra now passes a temp vreg in, rather
than requiring use of a fixed, non-allocable temp; tests have been
updated, and the runtime behavior is unchanged.

cranelift/codegen/src/isa/aarch64/abi.rs

@@ -544,6 +544,7 @@ impl ABIMachineImpl for AArch64MachineImpl {
  defs: Vec<Writable<Reg>>,
  loc: SourceLoc,
  opcode: ir::Opcode,
+ tmp: Writable<Reg>,
  ) -> SmallVec<[(/* is_safepoint = */ bool, Inst); 2]> {
  let mut insts = SmallVec::new();
  match &dest {
@@ -563,7 +564,7 @@ impl ABIMachineImpl for AArch64MachineImpl {
  insts.push((
  false,
  Inst::LoadExtName {
- rd: writable_spilltmp_reg(),
+ rd: tmp,
  name: Box::new(name.clone()),
  offset: 0,
  srcloc: loc,
@@ -573,7 +574,7 @@ impl ABIMachineImpl for AArch64MachineImpl {
  true,
  Inst::CallInd {
  info: Box::new(CallIndInfo {
- rn: spilltmp_reg(),
+ rn: tmp.to_reg(),
  uses,
  defs,
  loc,