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Use type inference a bit more now that we have the right From impls.
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@cfallin
cfallin committed Oct 26, 2023
1 parent a0cfee2 commit 72a09ec
Showing 1 changed file with 25 additions and 25 deletions.
50 changes: 25 additions & 25 deletions cranelift/codegen/src/isa/x64/pcc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,7 @@ pub(crate) fn check(
src1,
ref src2,
dst,
} => match *<&RegMemImm>::from(src2) {
} => match src2.into() {
RegMemImm::Reg { reg: src2 } => {
let bits = size.to_bits().into();
check_binop(
Expand Down Expand Up @@ -98,7 +98,7 @@ pub(crate) fn check(
src1,
ref src2,
dst,
} => match *<&RegMemImm>::from(src2) {
} => match src2.into() {
RegMemImm::Imm { simm32 } => {
let bits = size.to_bits().into();
check_unop(
Expand Down Expand Up @@ -132,7 +132,7 @@ pub(crate) fn check(
ref src2,
dst,
..
} => match <&RegMemImm>::from(src2) {
} => match src2.into() {
RegMemImm::Mem { ref addr } => {
let loaded = check_load(ctx, None, addr, vcode, size.to_type(), 64)?;
check_output(ctx, vcode, dst.to_writable_reg(), &[], |_vcode| {
Expand All @@ -159,7 +159,7 @@ pub(crate) fn check(
ref src2,
dst,
..
} => match <&RegMem>::from(src2) {
} => match src2.into() {
RegMem::Mem { ref addr } => {
let loaded = check_load(ctx, None, addr, vcode, size.to_type(), 64)?;
check_output(ctx, vcode, dst.to_writable_reg(), &[], |_vcode| {
Expand Down Expand Up @@ -187,7 +187,7 @@ pub(crate) fn check(
}
| Inst::UnaryRmRImmVex {
size, ref src, dst, ..
} => match <&RegMem>::from(src) {
} => match src.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, size.to_type(), 64)?;
check_output(ctx, vcode, dst.to_writable_reg(), &[], |_vcode| {
Expand All @@ -208,7 +208,7 @@ pub(crate) fn check(
dst_remainder,
..
} => {
match <&RegMem>::from(divisor) {
match divisor.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, size.to_type(), 64)?;
}
Expand All @@ -221,7 +221,7 @@ pub(crate) fn check(
Inst::Div8 {
dst, ref divisor, ..
} => {
match <&RegMem>::from(divisor) {
match divisor.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I8, 64)?;
}
Expand All @@ -239,7 +239,7 @@ pub(crate) fn check(
ref src2,
..
} => {
match <&RegMem>::from(src2) {
match src2.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, size.to_type(), 64)?;
}
Expand All @@ -255,7 +255,7 @@ pub(crate) fn check(
ref src2,
..
} => {
match <&RegMem>::from(src2) {
match src2.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, size.to_type(), 64)?;
}
Expand Down Expand Up @@ -299,7 +299,7 @@ pub(crate) fn check(
} => {
let from_bytes: u16 = ext_mode.src_size().into();
let to_bytes: u16 = ext_mode.dst_size().into();
match <&RegMem>::from(src) {
match src.into() {
RegMem::Reg { reg } => {
check_unop(ctx, vcode, 64, dst.to_writable_reg(), *reg, |src| {
let extended = ctx.uextend(src, from_bytes * 8, to_bytes * 8);
Expand Down Expand Up @@ -346,7 +346,7 @@ pub(crate) fn check(
ref src,
dst,
} => {
match <&RegMem>::from(src) {
match src.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, ext_mode.src_type(), 64)?;
}
Expand Down Expand Up @@ -386,7 +386,7 @@ pub(crate) fn check(
}

Inst::XmmRmiReg { dst, ref src2, .. } => {
match <&RegMemImm>::from(src2) {
match src2.into() {
RegMemImm::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I8X16, 128)?;
}
Expand All @@ -395,7 +395,7 @@ pub(crate) fn check(
ensure_no_fact(vcode, dst.to_writable_reg().to_reg())
}

Inst::CmpRmiR { size, ref src, .. } => match <&RegMemImm>::from(src) {
Inst::CmpRmiR { size, ref src, .. } => match src.into() {
RegMemImm::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, size.to_type(), 64)?;
Ok(())
Expand All @@ -413,7 +413,7 @@ pub(crate) fn check(
ref consequent,
..
} => {
match <&RegMem>::from(consequent) {
match consequent.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, size.to_type(), 64)?;
}
Expand All @@ -427,7 +427,7 @@ pub(crate) fn check(
ref consequent,
..
} => {
match <&RegMem>::from(consequent) {
match consequent.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I8X16, 128)?;
}
Expand All @@ -436,7 +436,7 @@ pub(crate) fn check(
ensure_no_fact(vcode, dst.to_writable_reg().to_reg())
}

Inst::Push64 { ref src } => match <&RegMemImm>::from(src) {
Inst::Push64 { ref src } => match src.into() {
RegMemImm::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I64, 64)?;
Ok(())
Expand All @@ -456,7 +456,7 @@ pub(crate) fn check(
| Inst::XmmUnaryRmRImm {
dst, src: ref src2, ..
} => {
match <&RegMem>::from(src2) {
match src2.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I8X16, 128)?;
}
Expand Down Expand Up @@ -494,7 +494,7 @@ pub(crate) fn check(
| Inst::XmmUnaryRmREvex {
dst, src: ref src2, ..
} => {
match <&RegMem>::from(src2) {
match src2.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I8X16, 128)?;
}
Expand All @@ -504,7 +504,7 @@ pub(crate) fn check(
}

Inst::XmmRmiRVex { dst, ref src2, .. } => {
match <&RegMemImm>::from(src2) {
match src2.into() {
RegMemImm::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I8X16, 128)?;
}
Expand All @@ -514,7 +514,7 @@ pub(crate) fn check(
}

Inst::XmmVexPinsr { dst, ref src2, .. } => {
match <&RegMem>::from(src2) {
match src2.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I64, 64)?;
}
Expand All @@ -530,7 +530,7 @@ pub(crate) fn check(
Inst::XmmToGprImmVex { dst, .. } => ensure_no_fact(vcode, dst.to_writable_reg().to_reg()),

Inst::GprToXmmVex { dst, ref src, .. } | Inst::GprToXmm { dst, ref src, .. } => {
match <&RegMem>::from(src) {
match src.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I64, 64)?;
}
Expand All @@ -552,7 +552,7 @@ pub(crate) fn check(

Inst::CvtIntToFloat { dst, ref src2, .. }
| Inst::CvtIntToFloatVex { dst, ref src2, .. } => {
match <&RegMem>::from(src2) {
match src2.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I64, 64)?;
}
Expand Down Expand Up @@ -601,7 +601,7 @@ pub(crate) fn check(

Inst::XmmMinMaxSeq { dst, .. } => ensure_no_fact(vcode, dst.to_writable_reg().to_reg()),

Inst::XmmCmpRmR { ref src, .. } => match <&RegMem>::from(src) {
Inst::XmmCmpRmR { ref src, .. } => match src.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I8X16, 128)?;
Ok(())
Expand All @@ -610,7 +610,7 @@ pub(crate) fn check(
},

Inst::XmmRmRImm { dst, ref src2, .. } => {
match <&RegMem>::from(src2) {
match src2.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I8X16, 128)?;
}
Expand Down Expand Up @@ -638,7 +638,7 @@ pub(crate) fn check(
}
| Inst::JmpUnknown {
target: ref dest, ..
} => match <&RegMem>::from(dest) {
} => match dest.into() {
RegMem::Mem { ref addr } => {
check_load(ctx, None, addr, vcode, I64, 64)?;
Ok(())
Expand Down

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