riscv64: Add vector mask note

bytecodealliance · May 20, 2023 · a5952ba · a5952ba
1 parent 1e40013
commit a5952ba
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/cranelift/codegen/src/isa/riscv64/inst_vector.isle b/cranelift/codegen/src/isa/riscv64/inst_vector.isle
@@ -522,6 +522,9 @@
 
 
 ;; Build a vector mask from a u64
+;; TODO: We should merge this with the `vconst` rules, and take advantage of
+;; the other existing `vconst` rules. One example is using `vmv.v.i` which
+;; can represent some of these masks.
 (decl gen_vec_mask (u64) Reg)
 
 ;; Materialize the mask into an X register, and move it into the bottom of