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Make formats less SIMD-specific #1770

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May 30, 2020
Merged

Make formats less SIMD-specific #1770

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b4e0cb9
Replace InsertLane format with TernaryImm8
abrown May 26, 2020
0b00e07
Replace ExtractLane format with BinaryImm8
abrown May 27, 2020
eb5efe4
Rename BinaryImm format to BinaryImm64
abrown May 27, 2020
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6 changes: 3 additions & 3 deletions cranelift/codegen/meta/src/isa/riscv/recipes.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ pub(crate) fn define(shared_defs: &SharedDefinitions, regs: &IsaRegs) -> RecipeG

// R-type with an immediate shift amount instead of rs2.
recipes.push(
EncodingRecipeBuilder::new("Rshamt", &formats.binary_imm, 4)
EncodingRecipeBuilder::new("Rshamt", &formats.binary_imm64, 4)
.operands_in(vec![gpr])
.operands_out(vec![gpr])
.emit("put_rshamt(bits, in_reg0, imm.into(), out_reg0, sink);"),
Expand All @@ -79,11 +79,11 @@ pub(crate) fn define(shared_defs: &SharedDefinitions, regs: &IsaRegs) -> RecipeG
);

recipes.push(
EncodingRecipeBuilder::new("Ii", &formats.binary_imm, 4)
EncodingRecipeBuilder::new("Ii", &formats.binary_imm64, 4)
.operands_in(vec![gpr])
.operands_out(vec![gpr])
.inst_predicate(InstructionPredicate::new_is_signed_int(
&*formats.binary_imm,
&*formats.binary_imm64,
"imm",
12,
0,
Expand Down
12 changes: 6 additions & 6 deletions cranelift/codegen/meta/src/isa/x86/instructions.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -283,7 +283,7 @@ pub(crate) fn define(
Packed Shuffle Doublewords -- copies data from either memory or lanes in an extended
register and re-orders the data according to the passed immediate byte.
"#,
&formats.extract_lane,
&formats.binary_imm8,
)
.operands_in(vec![a, i]) // TODO allow copying from memory here (need more permissive type than TxN)
.operands_out(vec![a]),
Expand Down Expand Up @@ -314,7 +314,7 @@ pub(crate) fn define(
The lane index, ``Idx``, is an immediate value, not an SSA value. It
must indicate a valid lane index for the type of ``x``.
"#,
&formats.extract_lane,
&formats.binary_imm8,
)
.operands_in(vec![x, Idx])
.operands_out(vec![a]),
Expand Down Expand Up @@ -342,9 +342,9 @@ pub(crate) fn define(
The lane index, ``Idx``, is an immediate value, not an SSA value. It
must indicate a valid lane index for the type of ``x``.
"#,
&formats.insert_lane,
&formats.ternary_imm8,
)
.operands_in(vec![x, Idx, y])
.operands_in(vec![x, y, Idx])
.operands_out(vec![a]),
);

Expand All @@ -369,9 +369,9 @@ pub(crate) fn define(
extracted from and which it is inserted to. This is similar to x86_pinsr but inserts
floats, which are already stored in an XMM register.
"#,
&formats.insert_lane,
&formats.ternary_imm8,
)
.operands_in(vec![x, Idx, y])
.operands_in(vec![x, y, Idx])
.operands_out(vec![a]),
);

Expand Down
8 changes: 4 additions & 4 deletions cranelift/codegen/meta/src/isa/x86/legalize.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -459,7 +459,7 @@ fn define_simd(shared: &mut SharedDefinitions, x86_instructions: &InstructionGro
// Move into the lowest 16 bits of an XMM register.
def!(a = scalar_to_vector(x)),
// Insert the value again but in the next lowest 16 bits.
def!(b = insertlane(a, uimm8_one, x)),
def!(b = insertlane(a, x, uimm8_one)),
// No instruction emitted; pretend this is an I32x4 so we can use PSHUFD.
def!(c = raw_bitcast_any16x8_to_i32x4(b)),
// Broadcast the bytes in the XMM register with PSHUFD.
Expand Down Expand Up @@ -493,7 +493,7 @@ fn define_simd(shared: &mut SharedDefinitions, x86_instructions: &InstructionGro
// Move into the lowest 64 bits of an XMM register.
def!(a = scalar_to_vector(x)),
// Move into the highest 64 bits of the same XMM register.
def!(y = insertlane(a, uimm8_one, x)),
def!(y = insertlane(a, x, uimm8_one)),
],
);
}
Expand Down Expand Up @@ -567,11 +567,11 @@ fn define_simd(shared: &mut SharedDefinitions, x86_instructions: &InstructionGro
// Use scalar operations to shift the first lane.
def!(a = extractlane(x, uimm8_zero)),
def!(b = sshr_scalar_lane0(a, y)),
def!(c = insertlane(x, uimm8_zero, b)),
def!(c = insertlane(x, b, uimm8_zero)),
// Do the same for the second lane.
def!(d = extractlane(x, uimm8_one)),
def!(e = sshr_scalar_lane1(d, y)),
def!(z = insertlane(c, uimm8_one, e)),
def!(z = insertlane(c, e, uimm8_one)),
],
);
}
Expand Down
52 changes: 26 additions & 26 deletions cranelift/codegen/meta/src/isa/x86/recipes.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -607,20 +607,20 @@ pub(crate) fn define<'shared>(
// XX /r with FPR ins and outs. A form with a byte immediate.
{
recipes.add_template_inferred(
EncodingRecipeBuilder::new("fa_ib", &formats.insert_lane, 2)
EncodingRecipeBuilder::new("fa_ib", &formats.ternary_imm8, 2)
.operands_in(vec![fpr, fpr])
.operands_out(vec![0])
.inst_predicate(InstructionPredicate::new_is_unsigned_int(
&*formats.insert_lane,
"lane",
&*formats.ternary_imm8,
"imm",
8,
0,
))
.emit(
r#"
{{PUT_OP}}(bits, rex2(in_reg1, in_reg0), sink);
modrm_rr(in_reg1, in_reg0, sink);
let imm:i64 = lane.into();
let imm: i64 = imm.into();
sink.put1(imm as u8);
"#,
),
Expand Down Expand Up @@ -907,11 +907,11 @@ pub(crate) fn define<'shared>(
// XX /n ib with 8-bit immediate sign-extended.
{
recipes.add_template_inferred(
EncodingRecipeBuilder::new("r_ib", &formats.binary_imm, 2)
EncodingRecipeBuilder::new("r_ib", &formats.binary_imm64, 2)
.operands_in(vec![gpr])
.operands_out(vec![0])
.inst_predicate(InstructionPredicate::new_is_signed_int(
&*formats.binary_imm,
&*formats.binary_imm64,
"imm",
8,
0,
Expand All @@ -928,11 +928,11 @@ pub(crate) fn define<'shared>(
);

recipes.add_template_inferred(
EncodingRecipeBuilder::new("f_ib", &formats.binary_imm, 2)
EncodingRecipeBuilder::new("f_ib", &formats.binary_imm64, 2)
.operands_in(vec![fpr])
.operands_out(vec![0])
.inst_predicate(InstructionPredicate::new_is_signed_int(
&*formats.binary_imm,
&*formats.binary_imm64,
"imm",
8,
0,
Expand All @@ -951,11 +951,11 @@ pub(crate) fn define<'shared>(
// XX /n id with 32-bit immediate sign-extended.
recipes.add_template(
Template::new(
EncodingRecipeBuilder::new("r_id", &formats.binary_imm, 5)
EncodingRecipeBuilder::new("r_id", &formats.binary_imm64, 5)
.operands_in(vec![gpr])
.operands_out(vec![0])
.inst_predicate(InstructionPredicate::new_is_signed_int(
&*formats.binary_imm,
&*formats.binary_imm64,
"imm",
32,
0,
Expand All @@ -977,20 +977,20 @@ pub(crate) fn define<'shared>(
// XX /r ib with 8-bit unsigned immediate (e.g. for pshufd)
{
recipes.add_template_inferred(
EncodingRecipeBuilder::new("r_ib_unsigned_fpr", &formats.extract_lane, 2)
EncodingRecipeBuilder::new("r_ib_unsigned_fpr", &formats.binary_imm8, 2)
.operands_in(vec![fpr])
.operands_out(vec![fpr])
.inst_predicate(InstructionPredicate::new_is_unsigned_int(
&*formats.extract_lane,
"lane",
&*formats.binary_imm8,
"imm",
8,
0,
)) // TODO if the format name is changed then "lane" should be renamed to something more appropriate--ordering mask? broadcast immediate?
))
.emit(
r#"
{{PUT_OP}}(bits, rex2(in_reg0, out_reg0), sink);
modrm_rr(in_reg0, out_reg0, sink);
let imm:i64 = lane.into();
let imm: i64 = imm.into();
sink.put1(imm as u8);
"#,
),
Expand All @@ -1001,17 +1001,17 @@ pub(crate) fn define<'shared>(
// XX /r ib with 8-bit unsigned immediate (e.g. for extractlane)
{
recipes.add_template_inferred(
EncodingRecipeBuilder::new("r_ib_unsigned_gpr", &formats.extract_lane, 2)
EncodingRecipeBuilder::new("r_ib_unsigned_gpr", &formats.binary_imm8, 2)
.operands_in(vec![fpr])
.operands_out(vec![gpr])
.inst_predicate(InstructionPredicate::new_is_unsigned_int(
&*formats.extract_lane, "lane", 8, 0,
&*formats.binary_imm8, "imm", 8, 0,
))
.emit(
r#"
{{PUT_OP}}(bits, rex2(out_reg0, in_reg0), sink);
modrm_rr(out_reg0, in_reg0, sink); // note the flipped register in the ModR/M byte
let imm:i64 = lane.into();
let imm: i64 = imm.into();
sink.put1(imm as u8);
"#,
), "size_with_inferred_rex_for_inreg0_outreg0"
Expand All @@ -1021,20 +1021,20 @@ pub(crate) fn define<'shared>(
// XX /r ib with 8-bit unsigned immediate (e.g. for insertlane)
{
recipes.add_template_inferred(
EncodingRecipeBuilder::new("r_ib_unsigned_r", &formats.insert_lane, 2)
EncodingRecipeBuilder::new("r_ib_unsigned_r", &formats.ternary_imm8, 2)
.operands_in(vec![fpr, gpr])
.operands_out(vec![0])
.inst_predicate(InstructionPredicate::new_is_unsigned_int(
&*formats.insert_lane,
"lane",
&*formats.ternary_imm8,
"imm",
8,
0,
))
.emit(
r#"
{{PUT_OP}}(bits, rex2(in_reg1, in_reg0), sink);
modrm_rr(in_reg1, in_reg0, sink);
let imm:i64 = lane.into();
let imm: i64 = imm.into();
sink.put1(imm as u8);
"#,
),
Expand Down Expand Up @@ -2855,12 +2855,12 @@ pub(crate) fn define<'shared>(

{
let has_small_offset =
InstructionPredicate::new_is_signed_int(&*formats.binary_imm, "imm", 8, 0);
InstructionPredicate::new_is_signed_int(&*formats.binary_imm64, "imm", 8, 0);

// XX /n, MI form with imm8.
recipes.add_template(
Template::new(
EncodingRecipeBuilder::new("rcmp_ib", &formats.binary_imm, 2)
EncodingRecipeBuilder::new("rcmp_ib", &formats.binary_imm64, 2)
.operands_in(vec![gpr])
.operands_out(vec![reg_rflags])
.inst_predicate(has_small_offset)
Expand All @@ -2878,12 +2878,12 @@ pub(crate) fn define<'shared>(
);

let has_big_offset =
InstructionPredicate::new_is_signed_int(&*formats.binary_imm, "imm", 32, 0);
InstructionPredicate::new_is_signed_int(&*formats.binary_imm64, "imm", 32, 0);

// XX /n, MI form with imm32.
recipes.add_template(
Template::new(
EncodingRecipeBuilder::new("rcmp_id", &formats.binary_imm, 5)
EncodingRecipeBuilder::new("rcmp_id", &formats.binary_imm64, 5)
.operands_in(vec![gpr])
.operands_out(vec![reg_rflags])
.inst_predicate(has_big_offset)
Expand Down
27 changes: 12 additions & 15 deletions cranelift/codegen/meta/src/shared/formats.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ use std::rc::Rc;

pub(crate) struct Formats {
pub(crate) binary: Rc<InstructionFormat>,
pub(crate) binary_imm: Rc<InstructionFormat>,
pub(crate) binary_imm64: Rc<InstructionFormat>,
pub(crate) branch: Rc<InstructionFormat>,
pub(crate) branch_float: Rc<InstructionFormat>,
pub(crate) branch_icmp: Rc<InstructionFormat>,
Expand All @@ -17,14 +17,13 @@ pub(crate) struct Formats {
pub(crate) cond_trap: Rc<InstructionFormat>,
pub(crate) copy_special: Rc<InstructionFormat>,
pub(crate) copy_to_ssa: Rc<InstructionFormat>,
pub(crate) extract_lane: Rc<InstructionFormat>,
pub(crate) binary_imm8: Rc<InstructionFormat>,
pub(crate) float_compare: Rc<InstructionFormat>,
pub(crate) float_cond: Rc<InstructionFormat>,
pub(crate) float_cond_trap: Rc<InstructionFormat>,
pub(crate) func_addr: Rc<InstructionFormat>,
pub(crate) heap_addr: Rc<InstructionFormat>,
pub(crate) indirect_jump: Rc<InstructionFormat>,
pub(crate) insert_lane: Rc<InstructionFormat>,
pub(crate) int_compare: Rc<InstructionFormat>,
pub(crate) int_compare_imm: Rc<InstructionFormat>,
pub(crate) int_cond: Rc<InstructionFormat>,
Expand All @@ -45,6 +44,7 @@ pub(crate) struct Formats {
pub(crate) store_complex: Rc<InstructionFormat>,
pub(crate) table_addr: Rc<InstructionFormat>,
pub(crate) ternary: Rc<InstructionFormat>,
pub(crate) ternary_imm8: Rc<InstructionFormat>,
pub(crate) trap: Rc<InstructionFormat>,
pub(crate) unary: Rc<InstructionFormat>,
pub(crate) unary_bool: Rc<InstructionFormat>,
Expand Down Expand Up @@ -76,7 +76,9 @@ impl Formats {

binary: Builder::new("Binary").value().value().build(),

binary_imm: Builder::new("BinaryImm").value().imm(&imm.imm64).build(),
binary_imm8: Builder::new("BinaryImm8").value().imm(&imm.uimm8).build(),

binary_imm64: Builder::new("BinaryImm64").value().imm(&imm.imm64).build(),

// The select instructions are controlled by the second VALUE operand.
// The first VALUE operand is the controlling flag which has a derived type.
Expand All @@ -88,23 +90,18 @@ impl Formats {
.typevar_operand(1)
.build(),

ternary_imm8: Builder::new("TernaryImm8")
.value()
.imm(&imm.uimm8)
.value()
.build(),

// Catch-all for instructions with many outputs and inputs and no immediate
// operands.
multiary: Builder::new("MultiAry").varargs().build(),

nullary: Builder::new("NullAry").build(),

insert_lane: Builder::new("InsertLane")
.value()
.imm_with_name("lane", &imm.uimm8)
.value()
.build(),

extract_lane: Builder::new("ExtractLane")
.value()
.imm_with_name("lane", &imm.uimm8)
.build(),

shuffle: Builder::new("Shuffle")
.value()
.value()
Expand Down
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