Implement fcvt_to_uint_sat (f32x4 -> i32x4) for x86 #1822
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| .as_any() | ||
| .downcast_ref::<isa::x86::Isa>() | ||
| .expect("the target ISA must be x86 at this point"); | ||
| if x86_isa.isa_flags.use_avx512vl_simd() || x86_isa.isa_flags.use_avx512f_simd() { |
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Are the rounding semantics of the two alternative implementations equivalent? For the short case, vcvtps2udq, the Intel manual says "When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits." The slow path appears to use cvtt2si (presumably, really, cvttps2pi), and all the tt variant conversion insns are round-towards-zero: "When a conversion is inexact, a truncated (round toward zero) result is returned."
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This is a good point: I had hoped MXCSR would have the right rounding mode but it does not. I added a run filetest that passes with the long sequence and fails with the AVX512 sequence: it looks like the machines running the CI have AVX512 and therefore fail. I started playing around with a new recipe that embeds the rounding control (e.g. EvexContext::RoundingRegToRegFP { rc: EvexRoundingControl::RZ } but this didn't immediately fix the test case (the emitted bytes aren't exactly right) so I will have to play around with this a bit more.
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This allows x86 machines with the right AVX features to lower fcvt_to_uint_sat.i32x4 to a single instruction.
This converts an `f32x4` into an `i32x4` (unsigned) with some rounding either by using an AVX512VL/F instruction--VCVTPS2UDQ--or a long sequence of SSE4.1 compatible instructions.
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Replacing this with #1990--I propose we look at the AVX512 lowering in a separate PR since it may get tricky (and this legalization is already tricky enough). |
This follows from #1821 and should be merged after that PR.[ready to review]Along the lines of #1820, this adds the necessary legalizations and instructions for enabling the Wasm SIMD spec tests with truncation instructions.