Detailed debug-info (DWARF) support in new backends (initially x64).

.github/workflows/main.yml

@@ -292,6 +292,14 @@ jobs:
  env:
  RUST_BACKTRACE: 1
 
+ # Test debug (DWARF) related functionality on new backend.
+ - run: |
+ sudo apt-get update && sudo apt-get install -y gdb
+ cargo test --features experimental_x64 test_debug_dwarf -- --ignored --test-threads 1 --test debug::
+ if: matrix.os == 'ubuntu-latest'
+ env:
+ RUST_BACKTRACE: 1
+
  # Build and test lightbeam. Note that
  # Lightbeam tests fail right now, but we don't want to block on that.
  - run: cargo build --package lightbeam

cranelift/codegen/Cargo.toml

@@ -74,7 +74,7 @@ all-arch = [
 ]
 
 # For dependent crates that want to serialize some parts of cranelift
-enable-serde = ["serde"]
+enable-serde = ["serde", "regalloc/enable-serde"]
 
 # Allow snapshotting regalloc test cases. Useful only to report bad register
 # allocation failures, or for regalloc.rs developers.

cranelift/codegen/src/context.rs

@@ -473,6 +473,7 @@ impl Context {
  Ok(build_value_labels_ranges::<ComparableSourceLoc>(
  &self.func,
  &self.regalloc,
+ self.mach_compile_result.as_ref(),
  isa,
  ))
  }

cranelift/codegen/src/ir/mod.rs

@@ -58,6 +58,7 @@ pub use crate::ir::table::TableData;
 pub use crate::ir::trapcode::TrapCode;
 pub use crate::ir::types::Type;
 pub use crate::ir::valueloc::{ArgumentLoc, ValueLoc};
+pub use crate::value_label::LabelValueLoc;
 pub use cranelift_codegen_shared::condcodes;
 
 use crate::binemit;

cranelift/codegen/src/isa/aarch64/inst/emit.rs

@@ -2371,6 +2371,9 @@ impl MachInstEmit for Inst {
  sink.bind_label(jump_around_label);
  }
  }
+ &Inst::ValueLabelMarker { .. } => {
+ // Nothing; this is only used to compute debug info.
+ }
  }
 
  let end_off = sink.cur_offset();

cranelift/codegen/src/isa/aarch64/inst/mod.rs

@@ -7,7 +7,7 @@ use crate::binemit::CodeOffset;
 use crate::ir::types::{
  B1, B128, B16, B32, B64, B8, F32, F64, FFLAGS, I128, I16, I32, I64, I8, I8X16, IFLAGS, R32, R64,
 };
-use crate::ir::{ExternalName, MemFlags, Opcode, SourceLoc, TrapCode, Type};
+use crate::ir::{ExternalName, MemFlags, Opcode, SourceLoc, TrapCode, Type, ValueLabel};
 use crate::isa::CallConv;
 use crate::machinst::*;
 use crate::{settings, CodegenError, CodegenResult};
@@ -1210,6 +1210,12 @@ pub enum Inst {
  /// The needed space before the next deadline.
  needed_space: CodeOffset,
  },
+
+ /// A definition of a value label.
+ ValueLabelMarker {
+ reg: Reg,
+ label: ValueLabel,
+ },
 }
 
 fn count_zero_half_words(mut value: u64, num_half_words: u8) -> usize {
@@ -2017,6 +2023,9 @@ fn aarch64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
  memarg_regs(mem, collector);
  }
  &Inst::VirtualSPOffsetAdj { .. } => {}
+ &Inst::ValueLabelMarker { reg, .. } => {
+ collector.add_use(reg);
+ }
  &Inst::EmitIsland { .. } => {}
  }
 }
@@ -2767,6 +2776,9 @@ fn aarch64_map_regs<RUM: RegUsageMapper>(inst: &mut Inst, mapper: &RUM) {
  }
  &mut Inst::VirtualSPOffsetAdj { .. } => {}
  &mut Inst::EmitIsland { .. } => {}
+ &mut Inst::ValueLabelMarker { ref mut reg, .. } => {
+ map_use(mapper, reg);
+ }
  }
 }
 
@@ -2962,6 +2974,17 @@ impl MachInst for Inst {
  fn ref_type_regclass(_: &settings::Flags) -> RegClass {
  RegClass::I64
  }
+
+ fn gen_value_label_marker(label: ValueLabel, reg: Reg) -> Self {
+ Inst::ValueLabelMarker { label, reg }
+ }
+
+ fn defines_value_label(&self) -> Option<(ValueLabel, Reg)> {
+ match self {
+ Inst::ValueLabelMarker { label, reg } => Some((*label, *reg)),
+ _ => None,
+ }
+ }
 }
 
 //=============================================================================
@@ -4071,6 +4094,10 @@ impl Inst {
  format!("virtual_sp_offset_adjust {}", offset)
  }
  &Inst::EmitIsland { needed_space } => format!("emit_island {}", needed_space),
+
+ &Inst::ValueLabelMarker { label, reg } => {
+ format!("value_label {:?}, {}", label, reg.show_rru(mb_rru))
+ }
  }
  }
 }

cranelift/codegen/src/isa/aarch64/mod.rs

@@ -79,6 +79,7 @@ impl MachBackend for AArch64Backend {
  frame_size,
  disasm,
  unwind_info,
+ value_labels_ranges: None,
  })
  }
 

cranelift/codegen/src/isa/arm32/mod.rs

@@ -74,6 +74,7 @@ impl MachBackend for Arm32Backend {
  frame_size,
  disasm,
  unwind_info: None,
+ value_labels_ranges: None,
  })
  }
 

cranelift/codegen/src/isa/mod.rs

@@ -325,6 +325,12 @@ pub trait TargetIsa: fmt::Display + Send + Sync {
  Err(RegisterMappingError::UnsupportedArchitecture)
  }
 
+ #[cfg(feature = "unwind")]
+ /// Map a regalloc::Reg to its corresponding DWARF register.
+ fn map_regalloc_reg_to_dwarf(&self, _: ::regalloc::Reg) -> Result<u16, RegisterMappingError> {
+ Err(RegisterMappingError::UnsupportedArchitecture)
+ }
+
  /// Returns an iterator over legal encodings for the instruction.
  fn legal_encodings<'a>(
  &'a self,

cranelift/codegen/src/isa/x64/inst/emit.rs

@@ -3029,6 +3029,10 @@ pub(crate) fn emit(
  sink.put1(0xff);
  sink.put1(0x17);
  }
+
+ Inst::ValueLabelMarker { .. } => {
+ // Nothing; this is only used to compute debug info.
+ }
  }
 
  state.clear_post_insn();

cranelift/codegen/src/isa/x64/inst/mod.rs

@@ -1,7 +1,7 @@
 //! This module defines x86_64-specific machine instruction types.
 
 use crate::binemit::{CodeOffset, StackMap};
-use crate::ir::{types, ExternalName, Opcode, SourceLoc, TrapCode, Type};
+use crate::ir::{types, ExternalName, Opcode, SourceLoc, TrapCode, Type, ValueLabel};
 use crate::isa::x64::abi::X64ABIMachineSpec;
 use crate::isa::x64::settings as x64_settings;
 use crate::isa::CallConv;
@@ -484,6 +484,9 @@ pub enum Inst {
  /// A Mach-O TLS symbol access. Returns address of the TLS
  /// symbol in rax.
  MachOTlsGetAddr { symbol: ExternalName },
+
+ /// A definition of a value label.
+ ValueLabelMarker { reg: Reg, label: ValueLabel },
 }
 
 pub(crate) fn low32_will_sign_extend_to_64(x: u64) -> bool {
@@ -544,7 +547,8 @@ impl Inst {
  | Inst::XmmMinMaxSeq { .. }
  | Inst::XmmUninitializedValue { .. }
  | Inst::ElfTlsGetAddr { .. }
- | Inst::MachOTlsGetAddr { .. } => None,
+ | Inst::MachOTlsGetAddr { .. }
+ | Inst::ValueLabelMarker { .. } => None,
 
  // These use dynamic SSE opcodes.
  Inst::GprToXmm { op, .. }
@@ -1800,6 +1804,10 @@ impl PrettyPrint for Inst {
  Inst::MachOTlsGetAddr { ref symbol } => {
  format!("macho_tls_get_addr {:?}", symbol)
  }
+
+ Inst::ValueLabelMarker { label, reg } => {
+ format!("value_label {:?}, {}", label, reg.show_rru(mb_rru))
+ }
  }
  }
 }
@@ -2071,6 +2079,10 @@ fn x64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
  collector.add_def(reg);
  }
  }
+
+ Inst::ValueLabelMarker { reg, .. } => {
+ collector.add_use(*reg);
+ }
  }
 }
 
@@ -2446,6 +2458,8 @@ fn x64_map_regs<RUM: RegUsageMapper>(inst: &mut Inst, mapper: &RUM) {
  dst.map_uses(mapper);
  }
 
+ Inst::ValueLabelMarker { ref mut reg, .. } => map_use(mapper, reg),
+
  Inst::Ret
  | Inst::EpiloguePlaceholder
  | Inst::JmpKnown { .. }
@@ -2536,6 +2550,25 @@ impl MachInst for Inst {
  }
  }
 
+ fn stack_op_info(&self) -> Option<MachInstStackOpInfo> {
+ match self {
+ Self::VirtualSPOffsetAdj { offset } => Some(MachInstStackOpInfo::NomSPAdj(*offset)),
+ Self::MovRM {
+ size: 8,
+ src,
+ dst: SyntheticAmode::NominalSPOffset { simm32 },
+ } => Some(MachInstStackOpInfo::StoreNomSPOff(*src, *simm32 as i64)),
+ Self::Mov64MR {
+ src: SyntheticAmode::NominalSPOffset { simm32 },
+ dst,
+ } => Some(MachInstStackOpInfo::LoadNomSPOff(
+ dst.to_reg(),
+ *simm32 as i64,
+ )),
+ _ => None,
+ }
+ }
+
  fn gen_move(dst_reg: Writable<Reg>, src_reg: Reg, ty: Type) -> Inst {
  let rc_dst = dst_reg.to_reg().get_class();
  let rc_src = src_reg.get_class();
@@ -2710,6 +2743,17 @@ impl MachInst for Inst {
  RegClass::I64
  }
 
+ fn gen_value_label_marker(label: ValueLabel, reg: Reg) -> Self {
+ Inst::ValueLabelMarker { label, reg }
+ }
+
+ fn defines_value_label(&self) -> Option<(ValueLabel, Reg)> {
+ match self {
+ Inst::ValueLabelMarker { label, reg } => Some((*label, *reg)),
+ _ => None,
+ }
+ }
+
  type LabelUse = LabelUse;
 }
 

cranelift/codegen/src/isa/x64/mod.rs

@@ -4,13 +4,14 @@ use self::inst::EmitInfo;
 
 use super::TargetIsa;
 use crate::ir::{condcodes::IntCC, Function};
+use crate::isa::unwind::systemv::RegisterMappingError;
 use crate::isa::x64::{inst::regs::create_reg_universe_systemv, settings as x64_settings};
 use crate::isa::Builder as IsaBuilder;
 use crate::machinst::{compile, MachBackend, MachCompileResult, TargetIsaAdapter, VCode};
 use crate::result::CodegenResult;
 use crate::settings::{self as shared_settings, Flags};
 use alloc::boxed::Box;
-use regalloc::{PrettyPrint, RealRegUniverse};
+use regalloc::{PrettyPrint, RealRegUniverse, Reg};
 use target_lexicon::Triple;
 
 mod abi;
@@ -60,6 +61,7 @@ impl MachBackend for X64Backend {
  let buffer = buffer.finish();
  let frame_size = vcode.frame_size();
  let unwind_info = vcode.unwind_info()?;
+ let value_labels_ranges = vcode.value_labels_ranges()?;
 
  let disasm = if want_disasm {
  Some(vcode.show_rru(Some(&create_reg_universe_systemv(flags))))
@@ -72,6 +74,7 @@ impl MachBackend for X64Backend {
  frame_size,
  disasm,
  unwind_info,
+ value_labels_ranges,
  })
  }
 
@@ -127,6 +130,11 @@ impl MachBackend for X64Backend {
  fn create_systemv_cie(&self) -> Option<gimli::write::CommonInformationEntry> {
  Some(inst::unwind::systemv::create_cie())
  }
+
+ #[cfg(feature = "unwind")]
+ fn map_reg_to_dwarf(&self, reg: Reg) -> Result<u16, RegisterMappingError> {
+ inst::unwind::systemv::map_reg(reg).map(|reg| reg.0)
+ }
 }
 
 /// Create a new `isa::Builder`.

cranelift/codegen/src/machinst/adapter.rs

@@ -10,6 +10,9 @@ use crate::settings::Flags;
 #[cfg(feature = "testing_hooks")]
 use crate::regalloc::RegDiversions;
 
+#[cfg(feature = "unwind")]
+use crate::isa::unwind::systemv::RegisterMappingError;
+
 use core::any::Any;
 use std::borrow::Cow;
 use std::fmt;
@@ -134,6 +137,11 @@ impl TargetIsa for TargetIsaAdapter {
  self.backend.create_systemv_cie()
  }
 
+ #[cfg(feature = "unwind")]
+ fn map_regalloc_reg_to_dwarf(&self, r: Reg) -> Result<u16, RegisterMappingError> {
+ self.backend.map_reg_to_dwarf(r)
+ }
+
  fn as_any(&self) -> &dyn Any {
  self as &dyn Any
  }