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riscv64: Initial SIMD Vector Implementation #6240

Merged
merged 14 commits into from
Apr 20, 2023
Merged
2 changes: 1 addition & 1 deletion ci/build-test-matrix.js
Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,7 @@ const array = [
"target": "riscv64gc-unknown-linux-gnu",
"gcc_package": "gcc-riscv64-linux-gnu",
"gcc": "riscv64-linux-gnu-gcc",
"qemu": "qemu-riscv64 -cpu rv64,zba=true,zbb=true,zbc=true,zbs=true,zbkb=true -L /usr/riscv64-linux-gnu",
"qemu": "qemu-riscv64 -cpu rv64,v=true,vlen=256,vext_spec=v1.0,zba=true,zbb=true,zbc=true,zbs=true,zbkb=true -L /usr/riscv64-linux-gnu",
"qemu_target": "riscv64-linux-user",
"name": "Test Linux riscv64",
"filter": "linux-riscv64",
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1 change: 1 addition & 0 deletions cranelift/codegen/build.rs
Original file line number Diff line number Diff line change
Expand Up @@ -274,6 +274,7 @@ fn get_isle_compilations(
prelude_isle.clone(),
prelude_lower_isle.clone(),
src_isa_risc_v.join("inst.isle"),
src_isa_risc_v.join("inst_vector.isle"),
src_isa_risc_v.join("lower.isle"),
],
untracked_inputs: vec![clif_lower_isle.clone()],
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28 changes: 28 additions & 0 deletions cranelift/codegen/src/isa/riscv64/inst.isle
Original file line number Diff line number Diff line change
Expand Up @@ -329,6 +329,31 @@
(guard_size u32)
(probe_count u32)
(tmp WritableReg))

(VecAluRRR
(op VecAluOpRRR)
(vd WritableReg)
(vs1 Reg)
(vs2 Reg)
(vstate VState))

(VecSetState
(rd WritableReg)
(vstate VState))

(VecLoad
(eew VecElementWidth)
(to WritableReg)
(from VecAMode)
(flags MemFlags)
(vstate VState))

(VecStore
(eew VecElementWidth)
(to VecAMode)
(from Reg)
(flags MemFlags)
(vstate VState))
))


Expand Down Expand Up @@ -711,6 +736,9 @@

;; ISA Extension helpers

(decl pure has_v () bool)
(extern constructor has_v has_v)

(decl pure has_zbkb () bool)
(extern constructor has_zbkb has_zbkb)

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80 changes: 1 addition & 79 deletions cranelift/codegen/src/isa/riscv64/inst/args.rs
Original file line number Diff line number Diff line change
Expand Up @@ -1668,55 +1668,6 @@ impl CsrAddress {
}
}

pub(crate) struct VType {
vma: bool,
vta: bool,
vsew: Vsew,
valmul: Vlmul,
}

impl VType {
fn as_u32(self) -> u32 {
self.valmul.as_u32()
| self.vsew.as_u32() << 3
| if self.vta { 1 << 7 } else { 0 }
| if self.vma { 1 << 8 } else { 0 }
}

const fn vill_bit() -> u64 {
1 << 63
}
}

enum Vlmul {
vlmul_1_div_8 = 0b101,
vlmul_1_div_4 = 0b110,
vlmul_1_div_2 = 0b111,
vlmul_1 = 0b000,
vlmul_2 = 0b001,
vlmul_4 = 0b010,
vlmul_8 = 0b011,
}

impl Vlmul {
fn as_u32(self) -> u32 {
self as u32
}
}

enum Vsew {
sew_8 = 0b000,
sew_16 = 0b001,
sew_32 = 0b010,
sew_64 = 0b011,
}

impl Vsew {
fn as_u32(self) -> u32 {
self as u32
}
}

impl CsrOP {
pub(crate) fn op_name(self) -> &'static str {
match self {
Expand Down Expand Up @@ -1754,40 +1705,11 @@ impl CsrOP {
if self.need_rs() {
reg_to_gpr_num(rs.unwrap())
} else {
zimm.unwrap().as_u32()
zimm.unwrap().bits()
}
}
}

enum Vxrm {
// round-to-nearest-up (add +0.5 LSB)
rnu = 0b00,
// round-to-nearest-even
rne = 0b01,
//round-down (truncate)
rdn = 0b10,
// round-to-odd (OR bits into LSB, aka "jam")
rod = 0b11,
}

impl Vxrm {
pub(crate) fn as_u32(self) -> u32 {
self as u32
}
}

pub(crate) struct Vcsr {
xvrm: Vxrm,
// Fixed-point accrued saturation flag
vxsat: bool,
}

impl Vcsr {
pub(crate) fn as_u32(self) -> u32 {
return if self.vxsat { 1 } else { 0 } | self.xvrm.as_u32();
}
}

///Atomic Memory ordering.
#[derive(Copy, Clone, Debug)]
pub enum AMO {
Expand Down
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