riscv64: Support non 128bit vector sizes

[afonso360]

👋 Hey,

This is a small follow up to #6240. This PR does a couple of things:

• We now recognize the Zvl* family of extensions, which really just specify the minimum size of a vector register.
• Instead of gating our vector lowerings on has_v and assuming 128 bit registers, we now allow lowering any size as long as they fit in a single register.
  • We switch the type extractor to ty_vec_fits_in_register which feels slightly neater than (if-let $true (has_v)) everywhere
• Also iadd uses fits_in_64 which also matches small vectors, so I switched the rules to using ty_int_ref_scalar_64 which only match scalars.

This isn't really required, but it's neat that we get all of these lowerings without pretty much any effort, so I figured it would be worth it.

[alexcrichton]

Oh oops my comments on #6268 are probably more appropriate over here

[alexcrichton]

Looks good to me!

Should zvl128b imply the v extension or vice-versa?

[afonso360]

V should imply zvl128b, but not vice-versa. We don't yet have presets for v, but that shouldn't be too difficult to add. I'll add that in this PR as well.

[alexcrichton]

Oh right yes, I forgot that has_* is (at least following other backends) intended to be an individual feature. Feel free to defer a v feature to a future PR, no need to have it as part of this one.