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riscv64: Delete CSR Instructions #6267

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Apr 23, 2023
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riscv64: Delete CSR Instructions #6267

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17 changes: 0 additions & 17 deletions cranelift/codegen/src/isa/riscv64/inst.isle
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Original file line number Diff line number Diff line change
Expand Up @@ -227,13 +227,6 @@
(x ValueRegs)
(y ValueRegs)
(ty Type))
;; risc-v csr operations.
(Csr
(csr_op CsrOP)
(rd WritableReg)
(rs OptionReg)
(imm OptionUimm5)
(csr CsrAddress))
;; an integer compare.
(Icmp
(cc IntCC)
Expand Down Expand Up @@ -369,15 +362,6 @@
(Trunc)
))

(type CsrOP (enum
(Csrrw)
(Csrrs)
(Csrrc)
(Csrrwi)
(Csrrsi)
(Csrrci)
))

(type IntSelectOP (enum
(Smax)
(Umax)
Expand Down Expand Up @@ -716,7 +700,6 @@
(type Imm20 (primitive Imm20))
(type Imm3 (primitive Imm3))
(type BranchTarget (primitive BranchTarget))
(type CsrAddress (primitive CsrAddress))
(type OptionFloatRoundingMode (primitive OptionFloatRoundingMode))
(type VecU8 (primitive VecU8))
(type AMO (primitive AMO))
Expand Down
71 changes: 0 additions & 71 deletions cranelift/codegen/src/isa/riscv64/inst/args.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1639,77 +1639,6 @@ impl IntSelectOP {
}
}

#[derive(Clone, Copy)]
pub enum CsrAddress {
Fcsr = 0x3,
Vstart = 0x8,
Vxsat = 0x9,
Vxrm = 0xa,
Vcsr = 0xf,
Vl = 0xc20,
Vtype = 0xc21,
Vlenb = 0xc22,
}

impl std::fmt::Debug for CsrAddress {
fn fmt(&self, f: &mut Formatter<'_>) -> Result {
write!(f, "0x{:x}", self.as_u32())
}
}

impl Display for CsrAddress {
fn fmt(&self, f: &mut Formatter<'_>) -> Result {
write!(f, "0x{:x}", self.as_u32())
}
}
impl CsrAddress {
pub(crate) fn as_u32(self) -> u32 {
self as u32
}
}

impl CsrOP {
pub(crate) fn op_name(self) -> &'static str {
match self {
CsrOP::Csrrw => "csrrw",
CsrOP::Csrrs => "csrrs",
CsrOP::Csrrc => "csrrc",
CsrOP::Csrrwi => "csrrwi",
CsrOP::Csrrsi => "csrrsi",
CsrOP::Csrrci => "csrrci",
}
}

pub(crate) const fn need_rs(self) -> bool {
match self {
CsrOP::Csrrw | CsrOP::Csrrs | CsrOP::Csrrc => true,
_ => false,
}
}
pub(crate) const fn op_code(self) -> u32 {
0b1110011
}

pub(crate) fn funct3(self) -> u32 {
match self {
CsrOP::Csrrw => 0b001,
CsrOP::Csrrs => 0b010,
CsrOP::Csrrc => 0b011,
CsrOP::Csrrwi => 0b101,
CsrOP::Csrrsi => 0b110,
CsrOP::Csrrci => 0b110,
}
}

pub(crate) fn rs1(self, rs: Option<Reg>, zimm: OptionUimm5) -> u32 {
if self.need_rs() {
reg_to_gpr_num(rs.unwrap())
} else {
zimm.unwrap().bits()
}
}
}

///Atomic Memory ordering.
#[derive(Copy, Clone, Debug)]
pub enum AMO {
Expand Down
18 changes: 0 additions & 18 deletions cranelift/codegen/src/isa/riscv64/inst/emit.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -445,7 +445,6 @@ impl Inst {
| Inst::Select { .. }
| Inst::AtomicCas { .. }
| Inst::IntSelect { .. }
| Inst::Csr { .. }
| Inst::Icmp { .. }
| Inst::SelectReg { .. }
| Inst::FcvtToInt { .. }
Expand Down Expand Up @@ -1662,23 +1661,6 @@ impl MachInstEmit for Inst {
gen_move(&dst, &y, sink, state);
sink.bind_label(label_done, &mut state.ctrl_plane);
}
&Inst::Csr {
csr_op,
rd,
rs,
imm,
csr,
} => {
let rs = rs.map(|r| allocs.next(r));
let rd = allocs.next_writable(rd);
let x = csr_op.op_code()
| reg_to_gpr_num(rd.to_reg()) << 7
| csr_op.funct3() << 12
| csr_op.rs1(rs, imm) << 15
| csr.as_u32() << 20;

sink.put4(x);
}

&Inst::SelectReg {
condition,
Expand Down
24 changes: 1 addition & 23 deletions cranelift/codegen/src/isa/riscv64/inst/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,7 @@ pub(crate) type VecWritableReg = Vec<Writable<Reg>>;

use crate::isa::riscv64::lower::isle::generated_code::MInst;
pub use crate::isa::riscv64::lower::isle::generated_code::{
AluOPRRI, AluOPRRR, AtomicOP, CsrOP, FClassResult, FFlagsException, FenceFm, FloatRoundOP,
AluOPRRI, AluOPRRR, AtomicOP, FClassResult, FFlagsException, FenceFm, FloatRoundOP,
FloatSelectOP, FpuOPRR, FpuOPRRR, FpuOPRRRR, IntSelectOP, LoadOP, MInst as Inst, StoreOP, FRM,
};

Expand Down Expand Up @@ -521,13 +521,6 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
}
}

&Inst::Csr { rd, rs, .. } => {
if let Some(rs) = rs {
collector.reg_use(rs);
}
collector.reg_def(rd);
}

&Inst::Icmp { rd, a, b, .. } => {
collector.reg_uses(a.regs());
collector.reg_uses(b.regs());
Expand Down Expand Up @@ -1313,21 +1306,6 @@ impl Inst {
)
}
}
&Inst::Csr {
csr_op,
rd,
rs,
imm,
csr,
} => {
let rs = rs.map_or("".into(), |r| format_reg(r, allocs));
let rd = format_reg(rd.to_reg(), allocs);
if csr_op.need_rs() {
format!("{} {},{},{}", csr_op.op_name(), rd, csr, rs)
} else {
format!("{} {},{},{}", csr_op.op_name(), rd, csr, imm.unwrap())
}
}
&Inst::FpuRRRR {
alu_op,
rd,
Expand Down