riscv64: Add VecALUImm instruction format
#6325
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| pub fn funct6(&self) -> u32 { | ||
| // See: https://github.com/riscv/riscv-v-spec/blob/master/inst-table.adoc | ||
| match self { | ||
| VecAluOpRRImm5::Vadd => 0b000000, |
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I don't know much about RISC-V, but should this AluOp be different than VecAluOpRRR or the same? The single data point of Vadd has the encodings the same, but I'm not sure if the pattern holds up elsewhere.
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Well, It is the same, but not all opcodes work on both formats. vadd works for both, but vsub does not have a vsub.vi format. It would be nice if we could share the funct6 mapping somehow, since it is exactly the same on both for the cases that do exist, I'm just not sure how.
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Ah ok makes sense, in that case sounds good to me to have a minor amount of duplication 👍
| // OPIVI | ||
| 0b011 |
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My curiosity has been piqued if you're willing to oblige -- according to this doc I see a bunch of V/X/I columns but I'm not sure how that translates to the encoding. Is there a different document that explains how these columns relate to the encoding?
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That table does not seem to be explained anywhere, which is weird. The closest thing is 10. Vector Arithmetic Instruction Formats which only really explains the format, but not the encoding in that table. The way I understand it is the following.
There are 3 columns, which correspond to the 3 columns for the minor opcodes at the top (i.e. OPIVV, OPIVX, OPMVX, etc..). The minor opcode corresponds to the funct3 field. (The exact encoding is specified here)
The minor opcodes correspond to the operands that instruction takes. OPIVV is for Vector/Vector instructions (i.e. vadd.vv), OPIVX is for Vector/X Register instructions (i.e. vadd.vx) and OPIVI is for Vector/Immediate instructions (i.e. vadd.vi) which is what is implemented in this PR.
I'm only planning on having 2 instruction formats, since OP*VV,OP*VX and OPFVF can share the same instruction format in cranelift. Just with an assert that we are using the correct regclass. OPIVI is the only special one here.
The big table displays the funct6 field. Take for example the vrsub instruction. It is in the leftmost column, and only has X and I formats. So we know that it only takes the minor opcode formats of OPIVX and OPIVI. vrsub itself has a funct6 of 0b000011 with both of those minor opcodes.
There are additional encoding spaces, at the bottom, but my understanding is that these are all OPIVI instructions and that encoding gets put in the immediate field (not 100% sure on this yet).
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I've also now put these into a VecOpCategory struct so that their encoding is somewhat centralized.
👋 Hey,
This PR adds a new vector instruction format
Vector+Imm. The encoding is exactly the same asv*.vvbut the second register is instead a 5 bit field. This immediate is signed for most ops, but unsigned for some.