riscv64: Implement a few misc SIMD instructions #6598
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alexcrichton
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| test run | ||
| target aarch64 | ||
| target s390x | ||
| target x86_64 ssse3 has_sse41=false |
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This may be a bit of a dated copy/paste now that SSSE3 is the baseline for x86_64 simd support, but I've only been doing this in tests that exercise post-SSE2 instructions which I'm not sure if select does, but basically it's ok to delete this line if you'd like
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👋 Hey,
This is a number of changes that are all quite small and unrelated to each other but allow us to enable a few more SIMD tests. Each commit is unrelated to other commits, so reviewing them individually might make more sense.
The vector select instruction is implemented the preexisting scalar version of the instruction that uses a conditional branch over a move instruction. Vector move instructions were implemented in #6568 so we just needed to allocate a vector register and the existing code already works!
None of these commits have any relation to the
memory64tests, I just tested enabling those and it looks like we already implement all required instructions.