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riscv64: Implement SIMD sqmul_round_sat and splat+mul instructions #6602

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merged 2 commits into from
Jun 19, 2023

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afonso360
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👋 Hey,

This PR Implements sqmul_round_sat, we have a dedicated instruction for this so it's fairly straight forward.

Additionally it also adds some variants of the existing multiplication instructions that splat one of the inputs. These were originally added before we had support for VX opcodes, and I've just noticed they were missing.

@afonso360 afonso360 added the cranelift:area:riscv64 Issues related to the RISC-V 64 backend. label Jun 18, 2023
@afonso360 afonso360 requested review from a team as code owners June 18, 2023 21:15
@afonso360 afonso360 requested review from fitzgen and removed request for a team June 18, 2023 21:15
@afonso360 afonso360 changed the title riscv64: Implement SIMD sqmul_round_sat and splat+imul instructions riscv64: Implement SIMD sqmul_round_sat and splat+mul instructions Jun 18, 2023
@github-actions github-actions bot added the cranelift Issues related to the Cranelift code generator label Jun 18, 2023
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@elliottt elliottt left a comment

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This looks good to me! The vx variants for some of the vector ops seem extremely useful!

@afonso360 afonso360 added this pull request to the merge queue Jun 19, 2023
Merged via the queue into bytecodealliance:main with commit 0e9ce4c Jun 19, 2023
@afonso360 afonso360 deleted the riscv-simd-extra-mul branch June 19, 2023 14:49
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2 participants