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Cranelift: Do not have any callee-save registers for the tail calling convention #6608

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merged 1 commit into from
Jun 21, 2023

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@fitzgen fitzgen commented Jun 20, 2023

That is, mark all allocatable registers as clobbered by tail calls.

Additionally, use (basically) all allocatable registers for passing arguments and returns. ("Basically" because we have to leave at least one register available to hold the callee address for indirect calls or else we'll get regalloc constraint errors.)

I could get three more argument registers on riscv if I refactored compute_arg_locs and/or did something similar to aarch64's compute_arg_locs_tail but it didn't seem worth the hassle.

@fitzgen fitzgen requested review from a team as code owners June 20, 2023 19:52
@fitzgen fitzgen requested review from abrown and jameysharp and removed request for a team and abrown June 20, 2023 19:52
@github-actions github-actions bot added cranelift Issues related to the Cranelift code generator cranelift:area:machinst Issues related to instruction selection and the new MachInst backend. cranelift:area:aarch64 Issues related to AArch64 backend. cranelift:area:x64 Issues related to x64 codegen labels Jun 20, 2023
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In the future it's expected that all wasm calls will move to the tail convention, right? If that's the case would it be possible to run a version of this through sightglass to see if it affects runtime benchmarks?

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fitzgen commented Jun 21, 2023

In the future it's expected that all wasm calls will move to the tail convention, right? If that's the case would it be possible to run a version of this through sightglass to see if it affects runtime benchmarks?

That is the eventual plan, and we will definitely do a sightglass run before switching over, but we aren't quite ready to do it yet.

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I don't much like the structure of this code; I know you've said you don't either. But this PR doesn't make it worse, so let's go with it.

I spent some time trying to figure out if there was more we could share between the register allocator configuration and these ABI bits, given that all allocatable registers are supposed to be clobbered in this ABI, but that didn't look straightforward.

As future work, I think there's something we can do with RA2's PRegSet to represent all of these different ABI-relevant sets of registers compactly; there's a popcount-like trick for finding the index of the Nth set bit that I think covers most of the uses we need here. (See the "Select the bit position (from the most-significant bit) with the given count (rank)" section of https://graphics.stanford.edu/~seander/bithacks.html.) But that's not necessary to land this.

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@fitzgen fitzgen enabled auto-merge June 21, 2023 19:42
@fitzgen fitzgen added this pull request to the merge queue Jun 21, 2023
Merged via the queue into bytecodealliance:main with commit 8118e5d Jun 21, 2023
@fitzgen fitzgen deleted the tail-no-callee-saves branch June 21, 2023 21:06
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