riscv64: Implement vector floating point rounding instructions #6920
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…odealliance#6920) * riscv64: Add CSR Instructions * riscv64: Add float to int vector instructions * cranelift: Split vector rounding mode tests * riscv64: Implement float rounding ops for vectors * riscv64: Update tests
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👋 Hey,
This PR Implements the floating point rounding instructions for SIMD values in the RISC-V backend. I'm not too familiar with the intricacies of this algorithm, I've mostly just copied what LLVM emits.
This PR also re-introduces CSR Instructions (deleted in #6267). CSR's are Control and Status Registers, which are used to hold architectural state such as Floating point round modes and Vector type state, etc..
Despite being part of the Zicsr extension, this extension is part of the minimum set of extensions that we need to function (i.e. it is required for floating point to work).